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52 lines
2.0 KiB
Systemverilog
52 lines
2.0 KiB
Systemverilog
///////////////////////////////////////////
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// regfile_p2r1w1bwen
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//
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// Written: Ross Thompson September 18, 2021
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// Modified: 2 port register file with 1 read and 1 write
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//
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module regfile_p2r1w1bwen #(parameter integer DEPTH = 10, parameter integer WIDTH = 4)
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(input logic clk,
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input logic we1,
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input logic [WIDTH-1:0] we1bit,
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input logic [DEPTH-1:0] ra1,
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output logic [WIDTH-1:0] rd1,
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input logic [DEPTH-1:0] wa1,
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input logic [WIDTH-1:0] wd1);
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logic [WIDTH-1:0] regs [2**DEPTH-1:0];
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integer i;
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always_ff @(posedge clk) begin
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if(we1) begin
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for (i=0; i < WIDTH; i++) begin
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if(we1bit[i]) begin
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regs[wa1][i] <= wd1[i];
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end
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end
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end
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end
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assign rd1 = regs[ra1];
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endmodule
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