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167 lines
7.4 KiB
Systemverilog
167 lines
7.4 KiB
Systemverilog
///////////////////////////////////////////
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// mmu.sv
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//
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// Written: david_harris@hmc.edu and kmacsaigoren@hmc.edu 4 June 2021
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// Modified:
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//
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// Purpose: Memory management unit, including TLB, PMA, PMP
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
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parameter IMMU = 0) (
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input logic clk, reset,
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// Current value of satp CSR (from privileged unit)
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input logic [`XLEN-1:0] SATP_REGW,
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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// Current privilege level of the processeor
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input logic [1:0] PrivilegeModeW,
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// 00 - TLB is not being accessed
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// 1x - TLB is accessed for a read (or an instruction)
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// x1 - TLB is accessed for a write
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// 11 - TLB is accessed for both read and write
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input logic DisableTranslation,
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// VAdr goes to the TLB only. Virtual if the TLB is active.
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// PAdr goes to address mux bypassing the TLB. PAdr used when there is no translation.
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// Comes from either the program address (instruction address or load/store address)
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// or from the hardware pagetable walker.
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// PAdr is intended to used as a phsycial address. Discarded by the address mux when translation is
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// performed.
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// PhysicalAddress is selected to be PAdr when no translation or the translated VAdr (TLBPAdr)
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// when there is translation.
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input logic [`PA_BITS-1:0] PAdr, // *** consider renaming this.
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input logic [`XLEN-1:0] VAdr,
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input logic [1:0] Size, // 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
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// Controls for writing a new entry to the TLB
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input logic [`XLEN-1:0] PTE,
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input logic [1:0] PageTypeWriteVal,
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input logic TLBWrite,
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// Invalidate all TLB entries
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input logic TLBFlush,
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// Physical address outputs
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output logic [`PA_BITS-1:0] PhysicalAddress,
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output logic TLBMiss,
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output logic Cacheable, Idempotent, AtomicAllowed,
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// Faults
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output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM,
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output logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,
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output logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
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// PMA checker signals
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input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0]
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);
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logic [`PA_BITS-1:0] TLBPAdr;
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// Translation lookaside buffer
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logic PMAInstrAccessFaultF, PMPInstrAccessFaultF;
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logic PMALoadAccessFaultM, PMPLoadAccessFaultM;
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logic PMAStoreAmoAccessFaultM, PMPStoreAmoAccessFaultM;
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logic DataMisalignedM;
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logic Translate;
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logic TLBHit;
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logic TLBPageFault;
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// only instantiate TLB if Virtual Memory is supported
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if (`VIRTMEM_SUPPORTED) begin:tlb
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logic ReadAccess, WriteAccess;
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assign ReadAccess = ExecuteAccessF | ReadAccessM; // execute also acts as a TLB read. Execute and Read are never active for the same MMU, so safe to mix pipestages
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assign WriteAccess = WriteAccessM;
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tlb #(.TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU))
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tlb(.clk, .reset,
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.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]),
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.SATP_ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]),
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.VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PrivilegeModeW, .ReadAccess, .WriteAccess,
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.DisableTranslation, .PTE, .PageTypeWriteVal,
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.TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit,
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.Translate, .TLBPageFault);
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end else begin:tlb// just pass address through as physical
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assign Translate = 0;
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assign TLBMiss = 0;
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assign TLBHit = 1; // *** is this necessary
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assign TLBPageFault = 0;
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end
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// If translation is occuring, select translated physical address from TLB
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// the lower 12 bits are the page offset. These are never changed from the orginal
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// non translated address.
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//mux2 #(`PA_BITS) addressmux(PAdr, TLBPAdr, Translate, PhysicalAddress);
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mux2 #(`PA_BITS-12) addressmux(PAdr[`PA_BITS-1:12], TLBPAdr[`PA_BITS-1:12], Translate, PhysicalAddress[`PA_BITS-1:12]);
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assign PhysicalAddress[11:0] = PAdr[11:0];
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///////////////////////////////////////////
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// Check physical memory accesses
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///////////////////////////////////////////
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pmachecker pmachecker(.PhysicalAddress, .Size,
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.AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
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.Cacheable, .Idempotent, .AtomicAllowed,
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.PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
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pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.ExecuteAccessF, .WriteAccessM, .ReadAccessM,
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.PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
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// If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
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// assign SquashBusAccess = PMASquashBusAccess | PMPSquashBusAccess;
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assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit);
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assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit);
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assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~(Translate & ~TLBHit);
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always_comb
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case(Size[1:0])
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2'b00: DataMisalignedM = 0; // lb, sb, lbu
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2'b01: DataMisalignedM = VAdr[0]; // lh, sh, lhu
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2'b10: DataMisalignedM = VAdr[1] | VAdr[0]; // lw, sw, flw, fsw, lwu
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2'b11: DataMisalignedM = |VAdr[2:0]; // ld, sd, fld, fsd
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endcase
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// If the CPU's (not HPTW's) request is a page fault.
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assign LoadMisalignedFaultM = DataMisalignedM & ReadAccessM;
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assign StoreAmoMisalignedFaultM = DataMisalignedM & (WriteAccessM | AtomicAccessM);
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// Specify which type of page fault is occurring
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assign InstrPageFaultF = TLBPageFault & ExecuteAccessF;
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assign LoadPageFaultM = TLBPageFault & ReadAccessM;
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assign StoreAmoPageFaultM = TLBPageFault & (WriteAccessM | AtomicAccessM);
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endmodule
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