cvw/examples/verilog/fulladder/fulladder.do
2022-01-10 16:15:05 +00:00

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# fulladder.do
# David_Harris@hmc.edu 10 January 2021
# compile, optimize, and start the simulation
vlog fulladder.sv
vopt +acc work.testbench -o workopt
vsim workopt
# Add waveforms and run the simulation
add wave *
run -all
view wave