mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
143 lines
4.1 KiB
Python
Executable File
143 lines
4.1 KiB
Python
Executable File
#!/usr/bin/env python3
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#########################################################################################
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# hw_test.py
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#
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# Written: matthew.n.otto@okstate.edu
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# Created: 19 April 2024
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#
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# Purpose: Send test commands to OpenOCD via local telnet connection
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#
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# A component of the CORE-V-WALLY configurable RISC-V project.
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# https:#github.com/openhwgroup/cvw
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#
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# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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#
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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#
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# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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# except in compliance with the License, or, at your option, the Apache License version 2.0. You
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# may obtain a copy of the License at
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#
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# https:#solderpad.org/licenses/SHL-2.1/
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#
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# Unless required by applicable law or agreed to in writing, any work distributed under the
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# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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# either express or implied. See the License for the specific language governing permissions
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# and limitations under the License.
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#########################################################################################
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import random
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import time
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import hw_debug_interface
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from hw_debug_interface import *
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random_stimulus = False
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def main():
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registers = dict.fromkeys(register_translations.keys(),[])
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reg_addrs = list(registers.keys())
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init()
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global XLEN
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XLEN = hw_debug_interface.XLEN
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reset_dm()
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reset_hart()
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time.sleep(70) # wait for OpenSBI
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halt()
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status()
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# dump data in all registers
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for r in reg_addrs:
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try:
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data = read_data(r)
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registers[r] = data
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print(f"{r}: {data}")
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except Exception as e:
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if e.args[0] == "exception": # Invalid register (not implemented)
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del registers[r]
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clear_abstrcmd_err()
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else:
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raise e
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input("Compare values to ILA, press any key to continue")
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# Write random data to all registers
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reg_addrs = list(registers.keys())
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if random_stimulus:
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random.shuffle(reg_addrs)
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test_reg_data = {}
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for r in reg_addrs:
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test_data = random_hex(r)
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try:
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write_data(r, test_data)
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test_reg_data[r] = test_data
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print(f"Writing {test_data} to {r}")
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except Exception as e:
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if e.args[0] == "not supported": # Register is read only
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del registers[r]
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clear_abstrcmd_err()
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else:
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raise e
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check_errors()
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# GPR X0 is always 0
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test_reg_data["X0"] = "0x" + "0"*(XLEN//4)
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# Confirm data was written correctly
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reg_addrs = list(registers.keys())
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if random_stimulus:
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random.shuffle(reg_addrs)
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for r in reg_addrs:
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try:
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rdata = read_data(r)
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except Exception as e:
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raise e
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if rdata != test_reg_data[r]:
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print(f"Error: register {r} read did not return correct data: {rdata} != {test_reg_data[r]}")
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else:
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print(f"Read {rdata} from {r}")
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# Return all registers to original state
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reg_addrs = list(registers.keys())
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for r in reg_addrs:
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print(f"Writing {registers[r]} to {r}")
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try:
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write_data(r, registers[r])
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except Exception as e:
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raise e
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# Confirm data was written correctly
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for r in reg_addrs:
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try:
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rdata = read_data(r)
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except Exception as e:
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raise e
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if rdata != registers[r]:
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raise Exception(f"Register {r} read did not return correct data: {rdata} != {registers[r]}")
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print("All writes successful")
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resume()
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status()
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def random_hex(reg_name):
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if reg_name in nonstandard_register_lengths:
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size = nonstandard_register_lengths[reg_name]
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pad = (XLEN-size) // 4
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else:
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size = XLEN
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pad = 0
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if random_stimulus:
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return f"0x{'0'*pad}{random.getrandbits(size):x}"
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else:
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data = 0xa5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5
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return f"0x{'0'*pad}{(data & (2**size-1)):x}"
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main()
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