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131 lines
7.5 KiB
Makefile
131 lines
7.5 KiB
Makefile
# David_Harris@hmc.edu 2023
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# Top-level Makefile for CORE-V-Wally
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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SIM = ${WALLY}/sim
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all:
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make install
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make riscof
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make testfloat
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# make verify
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make coverage
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make benchmarks
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# install copies over the Makefile.include from riscv-isa-sim
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# And corrects the TARGETDIR path and the RISCV_PREFIX
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install:
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# *** 1/15/23 dh: check if any of this is still needed
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#cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
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#sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include
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#echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
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##cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory
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##rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
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##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
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riscof:
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make -C sim
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testfloat:
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cd ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC; make
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cd ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC; make
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cd ${WALLY}/tests/fp; ./create_all_vectors.sh
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verify:
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cd ${SIM}; ./regression-wally
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cd ${SIM}/sim; ./sim-testfloat-batch all
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make imperasdv
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imperasdv:
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iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
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iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m
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imperasdv_cov:
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touch ${SIM}/seed0.txt
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echo "0" > ${SIM}/seed0.txt
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/cov/rv64gc_arch64i.ucdb --verbose
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose
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run-elf-cov.bash --elf ${WALLY}/tests/riscvdv/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${SIM}/questa/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose
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vcover report -details -html ${SIM}/questa/riscv.ucdb
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funcovreg:
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#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m --cover
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#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/I --cover
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#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege --cover
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#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/Q --cover
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rm -f ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/*/src/*/dut/my.elf
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iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I --cover
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vcover report -details -html ${SIM}/questa/riscv.ucdb
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# test_name=riscv_arithmetic_basic_test
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rvdv:
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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# run-elf.bash --seed ${SIM}/questa/seed0.txt --verbose --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/riscv.ucdb --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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cp ${SIM}/questa/riscv.ucdb ${SIM}/questa/regression_ucdbs/${test_name}.ucdb
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rvdv_regression:
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mkdir -p ${SIM}/questa/regression_logs
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mkdir -p ${SIM}/questa/regression_ucdbs
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cd ${SIM}/questa/regression_logs && rm -rf *
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cd ${SIM}/questa/regression_ucdbs && rm -rf *
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make rvdv test_name=riscv_arithmetic_basic_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_amo_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_ebreak_debug_mode_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_ebreak_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_arithmetic_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_mmu_stress_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_rand_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_full_interrupt_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_hint_instr_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_illegal_instr_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_invalid_csr_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_jump_stress_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_loop_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_machine_mode_rand_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_mmu_stress_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_no_fence_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_non_compressed_instr_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_pmp_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_privileged_mode_rand_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_rand_instr_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_rand_jump_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_sfence_exception_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_unaligned_load_store_test >> ${SIM}/questa/regression.log 2>&1
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rvdv_combine_coverage:
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mkdir -p ${SIM}/questa/regcov
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cd ${SIM}/questa/regcov && rm -rf *
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vcover merge ${SIM}/questa/regcov/regcov.ucdb ${SIM}/questa/regression_ucdbs/* -suppress 6854 -64
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vcover report -details -html ${SIM}/questa/regcov/regcov.ucdb
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vcover report ${SIM}/questa/regcov/regcov.ucdb -details -cvg > ${SIM}/questa/regcov/regcov.ucdb.log
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vcover report ${SIM}/questa/regcov/regcov.ucdb -testdetails -cvg > ${SIM}/questa/regcov/regcov.ucdb.testdetails.log
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vcover report ${SIM}/questa/regcov/regcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > ${SIM}/questa/regcov/regcov.ucdb.summary.log
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grep "Total Coverage By Instance" ${SIM}/questa/regcov/regcov.ucdb.log
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remove_rvdv_artifacts:
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rm ${SIM}/questa/riscv.ucdb ${SIM}/questa/regression.log covhtmlreport/ ${SIM}/questa/regression_logs/ ${SIM}/questa/regression_ucdbs/ ${SIM}/questa/regcov/ -rf
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collect_riscvdv_regression_coverage: remove_rvdv_artifacts rvdv_regression rvdv_combine_coverage
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coverage:
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regression-wally -coverage -fp
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benchmarks:
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make coremark
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make embench
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coremark:
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cd ${WALLY}/benchmarks/coremark; make; make run
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embench:
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cd ${WALLY}/benchmarks/embench; make; make run
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clean:
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make clean -C sim
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