James E. Stine 9954d16fc9 Add enhancements to integer divider including: ... - better comments - optimize FSM to end earlier - passes for 32-bit or 64-bit depending on parameter to intdiv Left div.bak in just in case have to revert back to original for now.		2021-05-31 09:12:21 -04:00
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cache	Reduced icache to 1 port memory.	2021-05-03 14:47:49 -05:00
dmem	progress on bus and lrsc	2021-04-26 07:43:16 -04:00
ebu	Clean up MMU code	2021-05-14 07:12:32 -04:00
fpu	classify unit created and passes imperas tests	2021-05-27 18:53:55 -04:00
generic	Modify elements of generics for LZD and shifter wrote for integer	2021-05-31 08:36:19 -04:00
hazard	turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)	2021-05-28 23:11:37 -04:00
ieu	All compare instructions pass imperas tests	2021-05-27 15:23:28 -04:00
ifu	turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)	2021-05-28 23:11:37 -04:00
mmu	Fix comment	2021-05-14 08:06:07 -04:00
muldiv	Add enhancements to integer divider including:	2021-05-31 09:12:21 -04:00
privileged	turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)	2021-05-28 23:11:37 -04:00
uncore	plic implementation optimizations	2021-05-19 18:10:48 +00:00
wally	turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)	2021-05-28 23:11:37 -04:00