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https://github.com/openhwgroup/cvw
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283 lines
11 KiB
Python
Executable File
283 lines
11 KiB
Python
Executable File
#!/usr/bin/env python3
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###########################################
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## CacheSim.py
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##
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## Written: lserafini@hmc.edu
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## Created: 27 March 2023
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## Modified: 12 April 2023
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##
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## Purpose: Simulate a L1 D$ or I$ for comparison with Wally
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##
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## A component of the CORE-V-WALLY configurable RISC-V project.
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##
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## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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##
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## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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##
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## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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## except in compliance with the License, or, at your option, the Apache License version 2.0. You
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## may obtain a copy of the License at
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##
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## https:##solderpad.org/licenses/SHL-2.1/
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##
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## Unless required by applicable law or agreed to in writing, any work distributed under the
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## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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## either express or implied. See the License for the specific language governing permissions
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## and limitations under the License.
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################################################################################################
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# how to invoke this simulator:
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# CacheSim.py <number of lines> <number of ways> <length of physical address> <length of tag> -f <log file> (-v)
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# so the default invocation for rv64gc is 'CacheSim.py 64 4 56 44 -f <log file>'
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# the log files to run this simulator on can be generated from testbench.sv
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# by setting I_CACHE_ADDR_LOGGER and/or D_CACHE_ADDR_LOGGER to 1 before running tests.
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# I (Lim) recommend logging a single set of tests (such as wally64priv) at a time.
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# This helps avoid unexpected logger behavior.
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# With verbose mode off, the simulator only reports mismatches between its and Wally's behavior.
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# With verbose mode on, the simulator logs each access into the cache.
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# Add -p or --perf to report the hit/miss ratio.
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# Add -d or --dist to report the distribution of loads, stores, and atomic ops.
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# These distributions may not add up to 100; this is because of flushes or invalidations.
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import sys
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import math
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import argparse
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import os
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class CacheLine:
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def __init__(self):
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self.tag = 0
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self.valid = False
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self.dirty = False
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def __str__(self):
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string = "(V: " + str(self.valid) + ", D: " + str(self.dirty)
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string += ", Tag: " + str(hex(self.tag)) + ")"
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return string
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def __repr__(self):
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return self.__str__()
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class Cache:
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def __init__(self, numsets, numways, addrlen, taglen):
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self.numways = numways
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self.numsets = numsets
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self.addrlen = addrlen
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self.taglen = taglen
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self.setlen = int(math.log(numsets, 2))
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self.offsetlen = self.addrlen - self.taglen - self.setlen
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self.ways = []
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for i in range(numways):
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self.ways.append([])
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for j in range(numsets):
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self.ways[i].append(CacheLine())
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self.pLRU = []
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for i in range(self.numsets):
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self.pLRU.append([0]*(self.numways-1))
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# flushes the cache by setting all dirty bits to False
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def flush(self):
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for way in self.ways:
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for line in way:
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line.dirty = False
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# invalidates the cache by setting all valid bits to False
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def invalidate(self):
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for way in self.ways:
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for line in way:
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line.valid = False
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# resets the pLRU to a fresh 2-D array of 0s
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def clear_pLRU(self):
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self.pLRU = []
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for i in range(self.numsets):
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self.pLRU.append([0]*(self.numways-1))
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# splits the given address into tag, set, and offset
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def splitaddr(self, addr):
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# no need for offset in the sim, but it's here for debug
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tag = addr >> (self.setlen + self.offsetlen) & int('1'*self.taglen, 2)
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setnum = (addr >> self.offsetlen) & int('1'*self.setlen, 2)
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offset = addr & int('1'*self.offsetlen, 2)
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return tag, setnum, offset
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# performs a cache access with the given address.
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# returns a character representing the outcome:
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# H/M/E/D - hit, miss, eviction, or eviction with writeback
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def cacheaccess(self, addr, write=False):
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tag, setnum, _ = self.splitaddr(addr)
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# check our ways to see if we have a hit
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for waynum in range(self.numways):
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line = self.ways[waynum][setnum]
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if line.tag == tag and line.valid:
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line.dirty = line.dirty or write
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self.update_pLRU(waynum, setnum)
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return 'H'
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# we didn't hit, but we may not need to evict.
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# check for an empty way line.
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for waynum in range(self.numways):
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line = self.ways[waynum][setnum]
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if not line.valid:
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line.tag = tag
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line.valid = True
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line.dirty = write
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self.update_pLRU(waynum, setnum)
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return 'M'
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# we need to evict. Select a victim and overwrite.
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victim = self.getvictimway(setnum)
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line = self.ways[victim][setnum]
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prevdirty = line.dirty
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line.tag = tag
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line.valid = True # technically redundant
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line.dirty = write
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self.update_pLRU(victim, setnum)
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return 'D' if prevdirty else 'E'
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# updates the psuedo-LRU tree for the given set
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# with an access to the given way
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def update_pLRU(self, waynum, setnum):
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if self.numways == 1:
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return
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tree = self.pLRU[setnum]
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bottomrow = (self.numways - 1)//2
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index = (waynum // 2) + bottomrow
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tree[index] = int(not (waynum % 2))
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while index > 0:
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parent = (index-1) // 2
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tree[parent] = index % 2
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index = parent
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# uses the psuedo-LRU tree to select
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# a victim way from the given set
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# returns the victim way as an integer
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def getvictimway(self, setnum):
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if self.numways == 1:
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return 0
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tree = self.pLRU[setnum]
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index = 0
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bottomrow = (self.numways - 1) // 2 #first index on the bottom row of the tree
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while index < bottomrow:
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if tree[index] == 0:
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# Go to the left child
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index = index*2 + 1
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else: #tree[index] == 1
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# Go to the right child
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index = index*2 + 2
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victim = (index - bottomrow)*2
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if tree[index] == 1:
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victim += 1
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return victim
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def __str__(self):
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string = ""
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for i in range(self.numways):
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string += "Way " + str(i) + ": "
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for line in self.ways[i]:
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string += str(line) + ", "
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string += "\n\n"
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return string
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def __repr__(self):
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return self.__str__()
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if __name__ == "__main__":
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parser = argparse.ArgumentParser(description="Simulates a L1 cache.")
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parser.add_argument('numlines', type=int, help="The number of lines per way (a power of 2)", metavar="L")
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parser.add_argument('numways', type=int, help="The number of ways (a power of 2)", metavar='W')
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parser.add_argument('addrlen', type=int, help="Length of the address in bits (a power of 2)", metavar="A")
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parser.add_argument('taglen', type=int, help="Length of the tag in bits", metavar="T")
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parser.add_argument('-f', "--file", required=True, help="Log file to simulate from")
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parser.add_argument('-v', "--verbose", action='store_true', help="verbose/full-trace mode")
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parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio")
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parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
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args = parser.parse_args()
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cache = Cache(args.numlines, args.numways, args.addrlen, args.taglen)
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extfile = os.path.expanduser(args.file)
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nofails = True
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if args.perf:
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hits = 0
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misses = 0
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if args.dist:
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loads = 0
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stores = 0
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atoms = 0
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totalops = 0
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with open(extfile, "r") as f:
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for ln in f:
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ln = ln.strip()
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lninfo = ln.split()
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if len(lninfo) < 3: #non-address line
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if len(lninfo) > 0 and (lninfo[0] == 'BEGIN' or lninfo[0] == 'TRAIN'):
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# currently BEGIN and END traces aren't being recorded correctly
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# trying TRAIN clears instead
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cache.invalidate() # a new test is starting, so 'empty' the cache
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cache.clear_pLRU()
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if args.verbose:
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print("New Test")
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else:
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if args.dist:
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totalops += 1
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if lninfo[1] == 'F':
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cache.flush()
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if args.verbose:
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print("F")
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elif lninfo[1] == 'I':
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cache.invalidate()
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if args.verbose:
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print("I")
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else:
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addr = int(lninfo[0], 16)
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iswrite = lninfo[1] == 'W' or lninfo[1] == 'A'
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result = cache.cacheaccess(addr, iswrite)
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if args.verbose:
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tag, setnum, offset = cache.splitaddr(addr)
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print(hex(addr), hex(tag), hex(setnum), hex(offset), lninfo[2], result)
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if args.perf:
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if result == 'H':
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hits += 1
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else:
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misses += 1
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if args.dist:
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if lninfo[1] == 'R':
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loads += 1
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elif lninfo[1] == 'W':
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stores += 1
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elif lninfo[1] == 'A':
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atoms += 1
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if not result == lninfo[2]:
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print("Result mismatch at address", lninfo[0]+ ". Wally:", lninfo[2]+", Sim:", result)
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nofails = False
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if args.dist:
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percent_loads = str(round(100*loads/totalops))
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percent_stores = str(round(100*stores/totalops))
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percent_atoms = str(round(100*atoms/totalops))
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print("This log had", percent_loads+"% loads,", percent_stores+"% stores, and", percent_atoms+"% atomic operations.")
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if args.perf:
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ratio = round(hits/misses,3)
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print("There were", hits, "hits and", misses, "misses. The hit/miss ratio was", str(ratio)+".")
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if nofails:
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print("SUCCESS! There were no mismatches between Wally and the sim.") |