Tejus Rao fb6a4bbbf0 added test cases for ADDW, SUBW, SLLW, SRLW, SRAW		2021-02-11 13:38:38 -05:00
..
testgen_footer.S	testgen-ADD-SUB initial untested	2021-01-19 22:58:56 -05:00
testgen_header.S	testgen-ADD-SUB initial untested	2021-01-19 22:58:56 -05:00
testgen-ADD-SUB.py	testgen-ADD-SUB working and testbench simualtes with new vectors for rv32 and rv64	2021-01-20 01:04:28 -05:00
testgen-ADDI-XORI-ORI-ANDI-SLTI.py	Adding I Type test cases from Lab 1	2021-02-10 09:39:43 -05:00
testgen-ADDIW-SLLIW-SRLIW-SRAIW.py	merge conflict?	2021-02-07 02:34:49 -05:00
testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py	added test cases for ADDW, SUBW, SLLW, SRLW, SRAW	2021-02-11 13:38:38 -05:00
testgen-JAL.py	JAL testing	2021-02-05 08:08:42 -05:00
testgen-LOAD.py	Add test vector set for load instructions	2021-02-06 13:05:59 -05:00
testgen-SLLI-SRLI-SRAI.py	Adding I Type test cases from Lab 1	2021-02-10 09:39:43 -05:00
testgen-SLTIU.py	Adding I Type test cases from Lab 1	2021-02-10 09:39:43 -05:00
testgen-STORE.py	Complete STORE tests	2021-02-04 15:38:22 -05:00