1
0
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
cvw/examples/verilog/fulladder/verilate

6 lines
327 B
Plaintext
Executable File

#verilator --timescale "1ns/1ns" --timing -cc --exe --build --top-module testbench fulladder.sv
#verilator --timescale "1ns/1ns" --timing -cc --exe --top-module testbench fulladder.sv
#verilator --binary --top-module testbench fulladder.sv
verilator --timescale "1ns/1ns" --timing --binary --top-module testbench fulladder.sv