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59 lines
1.6 KiB
Systemverilog
59 lines
1.6 KiB
Systemverilog
///////////////////////////////////////////
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// satCounter2.sv
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//
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// Written: Ross Thomposn
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// Email: ross1728@gmail.com
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// Created: February 13, 2021
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// Modified:
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//
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// Purpose: 2 bit starting counter
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module satCounter2
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(input logic BrDir,
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input logic [1:0] OldState,
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output logic [1:0] NewState
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);
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always_comb begin
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case(OldState)
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2'b00: begin
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if(BrDir) NewState = 2'b01;
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else NewState = 2'b00;
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end
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2'b01: begin
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if(BrDir) NewState = 2'b10;
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else NewState = 2'b00;
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end
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2'b10: begin
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if(BrDir) NewState = 2'b11;
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else NewState = 2'b01;
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end
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2'b11: begin
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if(BrDir) NewState = 2'b11;
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else NewState = 2'b10;
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end
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endcase
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end
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endmodule
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