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https://github.com/openhwgroup/cvw
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51 lines
1.2 KiB
Makefile
Executable File
51 lines
1.2 KiB
Makefile
Executable File
#
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# Makefile for synthesis
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#
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NAME := synth
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# defaults
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export DESIGN ?= wallypipelinedcore
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export FREQ ?= 500
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export CONFIG ?= rv32e
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# sky130 and sky90 presently supported
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export TECH ?= sky130
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# MAXCORES allows parallel compilation, which is faster but less CPU-efficient
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# Avoid when doing sweeps of many optimization points in parallel
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export MAXCORES ?= 4
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# MAXOPT turns on flattening, boundary optimization, and retiming
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# The output netlist is hard to interpret, but significantly better PPA
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export MAXOPT ?= 0
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time := $(shell date +%F-%H-%M)
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hash := $(shell git rev-parse --short HEAD)
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export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(hash)
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export SAIFPOWER ?= 0
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default:
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@echo "Basic synthesis procedure for OSU/HMC/UNLV:"
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@echo " adapt Makefile to your liking..."
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@echo
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synth:
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@echo "DC Synthesis"
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@mkdir -p hdl/
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@mkdir -p $(OUTPUTDIR)
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@mkdir -p $(OUTPUTDIR)/reports
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@mkdir -p $(OUTPUTDIR)/mapped
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@mkdir -p $(OUTPUTDIR)/unmapped
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ifeq ($(SAIFPOWER), 1)
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cp -f ../pipelined/regression/power.saif .
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endif
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dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
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clean:
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rm -rf alib-52 WORK analyzed $(NAME).out
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rm -f hdl/*
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rm -f default.svf
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rm -f command.log
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rm -f filenames*.log
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rm -f power.saif
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