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https://github.com/openhwgroup/cvw
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112 lines
4.1 KiB
Systemverilog
112 lines
4.1 KiB
Systemverilog
///////////////////////////////////////////
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// gpio.sv
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//
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// Written: David_Harris@hmc.edu 14 January 2021
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// Modified:
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//
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// Purpose: General Purpose I/O peripheral
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// See FE310-G002-Manual-v19p05 for specifications
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// No interrupts, drive strength, or pull-ups supported
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module gpio (
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input logic clk, reset,
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input logic [1:0] MemRWgpioM,
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// input logic [7:0] ByteMaskM,
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input logic [7:0] AdrM,
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input logic [`XLEN-1:0] MaskedWriteDataM,
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output logic [`XLEN-1:0] RdGPIOM,
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input logic [31:0] GPIOPinsIn,
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output logic [31:0] GPIOPinsOut, GPIOPinsEn);
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logic [31:0] INPUT_VAL, INPUT_EN, OUTPUT_EN, OUTPUT_VAL;
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logic [7:0] entry;
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logic memread, memwrite;
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assign memread = MemRWgpioM[1];
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assign memwrite = MemRWgpioM[0];
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// word aligned reads
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generate
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if (`XLEN==64)
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assign #2 entry = {AdrM[7:3], 3'b000};
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else
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assign #2 entry = {AdrM[7:2], 2'b00};
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endgenerate
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generate
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if (`GPIO_LOOPBACK_TEST) // connect OUT to IN for loopback testing
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assign INPUT_VAL = GPIOPinsOut & INPUT_EN & OUTPUT_EN;
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else
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assign INPUT_VAL = GPIOPinsIn & INPUT_EN;
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endgenerate
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assign GPIOPinsOut = OUTPUT_VAL;
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assign GPIOPinsEn = OUTPUT_EN;
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// register access
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generate
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if (`XLEN==64) begin
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always_comb begin
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case(entry)
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8'h00: RdGPIOM = {INPUT_EN, INPUT_VAL};
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8'h08: RdGPIOM = {OUTPUT_VAL, OUTPUT_EN};
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8'h40: RdGPIOM = 0; // OUT_XOR reads as 0
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default: RdGPIOM = 0;
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endcase
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end
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always_ff @(posedge clk or posedge reset)
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if (reset) begin
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INPUT_EN <= 0;
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OUTPUT_EN <= 0;
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OUTPUT_VAL <= 0; // spec indicates synchronous reset (software control)
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end else if (memwrite) begin
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if (entry == 8'h00) INPUT_EN <= MaskedWriteDataM[63:32];
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if (entry == 8'h08) {OUTPUT_VAL, OUTPUT_EN} <= MaskedWriteDataM;
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if (entry == 8'h40) OUTPUT_VAL <= OUTPUT_VAL ^ MaskedWriteDataM[31:0]; // OUT_XOR
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end
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end else begin // 32-bit
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always_comb begin
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case(entry)
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8'h00: RdGPIOM = INPUT_VAL;
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8'h04: RdGPIOM = INPUT_EN;
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8'h08: RdGPIOM = OUTPUT_EN;
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8'h0C: RdGPIOM = OUTPUT_VAL;
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8'h40: RdGPIOM = 0; // OUT_XOR reads as 0
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default: RdGPIOM = 0;
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endcase
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end
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always_ff @(posedge clk or posedge reset)
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if (reset) begin
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INPUT_EN <= 0;
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OUTPUT_EN <= 0;
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//OUTPUT_VAL <= 0;// spec indicates synchronous rset (software control)
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end else if (memwrite) begin
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if (entry == 8'h04) INPUT_EN <= MaskedWriteDataM;
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if (entry == 8'h08) OUTPUT_EN <= MaskedWriteDataM;
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if (entry == 8'h0C) OUTPUT_VAL <= MaskedWriteDataM;
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if (entry == 8'h40) OUTPUT_VAL <= OUTPUT_VAL ^ MaskedWriteDataM; // OUT_XOR
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end
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end
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endgenerate
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endmodule
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