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https://github.com/openhwgroup/cvw
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42 lines
907 B
Makefile
42 lines
907 B
Makefile
# David_Harris@hmc.edu 2023
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# Top-level Makefile for CORE-V-Wally
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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MAKEFLAGS += --output-sync --no-print-directory
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SIM = ${WALLY}/sim
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.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage clean
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all: riscof testfloat combined_IF_vectors zsbl coverage # benchmarks
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# riscof builds the riscv-arch-test and wally-riscv-arch-test suites
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riscof:
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$(MAKE) -C sim
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testfloat:
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$(MAKE) -C ${WALLY}/tests/fp vectors
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combined_IF_vectors: testfloat riscof
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$(MAKE) -C ${WALLY}/tests/fp combined_IF_vectors
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zsbl:
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$(MAKE) -C ${WALLY}/fpga/zsbl
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benchmarks:
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$(MAKE) coremark
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$(MAKE) embench
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coremark:
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cd ${WALLY}/benchmarks/coremark; $(MAKE); $(MAKE) run
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embench:
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cd ${WALLY}/benchmarks/embench; $(MAKE); $(MAKE) run
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coverage:
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$(MAKE) -C tests/coverage
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clean:
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$(MAKE) clean -C sim
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$(MAKE) clean -C ${WALLY}/tests/fp
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