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https://github.com/openhwgroup/cvw
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135 lines
4.9 KiB
Systemverilog
135 lines
4.9 KiB
Systemverilog
///////////////////////////////////////////
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// 2 port sram.
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//
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// Written: ross1728@gmail.com May 3, 2021
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// Two port SRAM 1 read port and 1 write port.
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// When clk rises Addr and LineWriteData are sampled.
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// Following the clk edge read data is output from the sampled Addr.
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// Write
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// Modified: james.stine@okstate.edu Feb 1, 2023
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// Integration of memories
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//
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// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
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`include "wally-config.vh"
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module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
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input logic clk,
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input logic ce1, ce2,
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input logic [$clog2(DEPTH)-1:0] ra1,
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input logic [WIDTH-1:0] wd2,
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input logic [$clog2(DEPTH)-1:0] wa2,
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input logic we2,
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input logic [(WIDTH-1)/8:0] bwe2,
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output logic [WIDTH-1:0] rd1
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);
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logic [WIDTH-1:0] mem[DEPTH-1:0];
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localparam SRAMWIDTH = 32;
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localparam SRAMNUMSETS = SRAMWIDTH/WIDTH;
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// ***************************************************************************
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// TRUE Smem macro
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// ***************************************************************************
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if (`USE_SRAM == 1 && WIDTH == 68 && DEPTH == 1024) begin
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ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk),
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.CEBA(~ce1), .CEBB(~ce2),
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.WEBA('0), .WEBB(~we2),
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.AA(ra1), .AB(wa2),
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.DA('0),
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.DB(wd2),
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.BWEBA('0), .BWEBB('1),
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.QA(rd1),
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.QB());
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end else if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin
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ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk),
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.CEBA(~ce1), .CEBB(~ce2),
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.WEBA('0), .WEBB(~we2),
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.AA(ra1), .AB(wa2),
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.DA('0),
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.DB(wd2),
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.BWEBA('0), .BWEBB('1),
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.QA(rd1),
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.QB());
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end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin
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logic [SRAMWIDTH-1:0] SRAMReadData;
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logic [SRAMWIDTH-1:0] SRAMWriteData;
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logic [SRAMWIDTH-1:0] RD1Sets[SRAMNUMSETS-1:0];
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logic [SRAMNUMSETS-1:0] SRAMBitMaskPre;
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logic [SRAMWIDTH-1:0] SRAMBitMask;
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logic [$clog2(DEPTH)-1:0] RA1Q;
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onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre);
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genvar index;
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for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux
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assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)];
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assign SRAMWriteData[index*2+1:index*2] = wd2;
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assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}};
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end
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flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q);
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assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]];
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ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk),
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.CEBA(~ce1), .CEBB(~ce2),
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.WEBA('0), .WEBB(~we2),
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.AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
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.AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
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.DA('0),
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.DB(SRAMWriteData),
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.BWEBA('0), .BWEBB(SRAMBitMask),
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.QA(SRAMReadData),
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.QB());
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end else begin
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// ***************************************************************************
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// READ first SRAM model
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// ***************************************************************************
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integer i;
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// Read
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always_ff @(posedge clk)
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if(ce1) rd1 <= #1 mem[ra1];
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// Write divided into part for bytes and part for extra msbs
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if(WIDTH >= 8)
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always @(posedge clk)
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if (ce2 & we2)
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for(i = 0; i < WIDTH/8; i++)
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if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
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if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
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always @(posedge clk)
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if (ce2 & we2 & bwe2[WIDTH/8])
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mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
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end
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endmodule
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