cvw/fpga/constraints
2024-08-23 17:18:47 -07:00
..
artyddr3.ucf Added more support for Arty A7 board. 2023-04-10 16:01:17 -05:00
constraints-ArtyA7.xdc On the way to making vcu108 work again. 2024-08-23 14:45:22 -07:00
constraints-vcu108.xdc VCU108 now boot linux at 50MHz! 2024-08-23 17:18:47 -07:00
constraints-vcu118.xdc Pushed vcu118 to 71MHz. 2023-08-25 17:04:50 -05:00
debug2.xdc Merge branch 'boot' into mergeBoot 2023-07-21 17:43:45 -05:00
debug4.xdc Added help option to the flash-sd script. 2023-08-22 13:37:33 -05:00
debug6.xdc The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file. 2024-05-30 15:48:27 -05:00
marked_debug_all.txt The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file. 2024-05-30 15:48:27 -05:00
marked_debug_rvvi.txt More updates to fpga IP module names. 2024-08-22 14:31:39 -07:00
marked_debug_small.txt Updated artyA7 debugger to match book. 2023-08-21 14:35:42 -05:00
marked_debug.txt VCU108 is not synthesizing at 50MHz. Still running into a few problems 2024-08-23 16:17:15 -07:00
small-debug-rvvi.xdc Updated for a better ILA rvvi debugger. 2024-07-22 17:44:04 -05:00
small-debug.xdc Now have configurations to switch between supporting RVVI over ethernet. 2024-07-22 10:51:13 -05:00
vcu-small-debug.xdc VCU108 is not synthesizing at 50MHz. Still running into a few problems 2024-08-23 16:17:15 -07:00