mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 21:14:37 +00:00
127 lines
5.1 KiB
Tcl
127 lines
5.1 KiB
Tcl
# start by reading in all the IP blocks generated by vivado
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set partNumber $::env(XILINX_PART)
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set boardName $::env(XILINX_BOARD)
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set boardSubName [lindex [split ${boardName} :] 1]
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set board $::env(board)
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set ipName WallyFPGA
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create_project $ipName . -force -part $partNumber
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if {$boardName!="ArtyA7"} {
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set_property board_part $boardName [current_project]
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}
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# read package first
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read_verilog -sv ../src/CopiedFiles_do_not_add_to_repo/cvw.sv
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read_verilog -sv ../src/wallypipelinedsocwrapper.sv
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# then read top level
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if {$board=="ArtyA7"} {
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read_verilog {../src/fpgaTopArtyA7.v}
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} else {
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read_verilog {../src/fpgaTop.v}
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}
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# read in ip
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read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci
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read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci
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read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci
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# Added crossbar - Jacob Pease <2023-01-12 Thu>
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read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci
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read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci
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read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci
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read_ip IP/xlnx_axi_prtcl_conv.srcs/sources_1/ip/xlnx_axi_prtcl_conv/xlnx_axi_prtcl_conv.xci
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if {$board=="ArtyA7"} {
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read_ip IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/xlnx_ddr3.xci
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read_ip IP/xlnx_mmcm.srcs/sources_1/ip/xlnx_mmcm/xlnx_mmcm.xci
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} else {
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read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
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}
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# read in all other rtl
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read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
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# *** Once the sdc is updated to use ahb changes these to system verilog.
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read_verilog [glob -type f ../src/axi_sdc_controller.v]
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read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_cmd_master.v]
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read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_cmd_serial_host.v]
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read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_master.v]
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read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_serial_host.v]
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set_property include_dirs {../../config/fpga ../../config/shared ../../addins/vivado-risc-v/sdc} [current_fileset]
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if {$board=="ArtyA7"} {
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add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
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set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc]
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} else {
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add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
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set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc]
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}
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# define top level
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set_property top fpgaTop [current_fileset]
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update_compile_order -fileset sources_1
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# This is important as the ddr3/4 IP contains the generate clock constraint which the user constraints depend on.
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exec mkdir -p reports/
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exec rm -rf reports/*
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report_compile_order -constraints > reports/compile_order.rpt
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# this is elaboration not synthesis.
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synth_design -rtl -name rtl_1 -flatten_hierarchy none
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report_clocks -file reports/clocks.rpt
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# Temp
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set_param messaging.defaultLimit 100000
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# this does synthesis?
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launch_runs synth_1 -jobs 16
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wait_on_run synth_1
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open_run synth_1
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check_timing -verbose -file reports/check_timing.rpt
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report_timing -max_paths 10 -nworst 10 -delay_type max -sort_by slack -file reports/timing_WORST_10.rpt
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report_timing -nworst 1 -delay_type max -sort_by group -file reports/timing.rpt
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report_utilization -hierarchical -file reports/utilization.rpt
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report_cdc -file reports/cdc.rpt
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report_clock_interaction -file reports/clock_interaction.rpt
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write_verilog -force -mode funcsim sim/syn-funcsim.v
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if {$board=="ArtyA7"} {
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source ../constraints/small-debug.xdc
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} else {
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# source ../constraints/vcu-small-debug.xdc
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source ../constraints/debug4.xdc
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}
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# set for RuntimeOptimized implementation
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#set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
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#set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
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launch_runs impl_1 -jobs 16
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wait_on_run impl_1
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launch_runs impl_1 -to_step write_bitstream
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wait_on_run impl_1
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open_run impl_1
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# output Verilog netlist + SDC for timing simulation
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exec mkdir -p sim/
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exec rm -rf sim/*
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write_verilog -force -mode funcsim sim/imp-funcsim.v
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write_verilog -force -mode timesim sim/imp-timesim.v
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write_sdf -force sim/imp-timesim.sdf
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# reports
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check_timing -file reports/imp_check_timing.rpt
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report_timing -max_paths 10 -nworst 10 -delay_type max -sort_by slack -file reports/imp_timing_WORST_10.rpt
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report_timing -nworst 1 -delay_type max -sort_by group -file reports/imp_timing.rpt
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report_utilization -hierarchical -file reports/imp_utilization.rpt
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