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38 lines
1.1 KiB
Systemverilog
38 lines
1.1 KiB
Systemverilog
`include "wally-config.vh"
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module resultsign(
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input logic [2:0] FrmM,
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input logic PSgnM, ZSgnEffM,
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input logic ZInfM,
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input logic InfIn,
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input logic FmaOp,
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input logic [`NE+1:0] SumExp,
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input logic SumZero,
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input logic Mult,
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input logic Round,
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input logic Sticky,
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input logic RoundSgn,
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output logic ResSgn
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);
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logic ZeroSgn;
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logic InfSgn;
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logic Underflow;
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// logic ResultSgnTmp;
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// Determine the sign if the sum is zero
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// if cancelation then 0 unless round to -infinity
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// if multiply then Psgn
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// otherwise psign
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assign Underflow = SumExp[`NE+1] | ((SumExp == 0) & (Round|Sticky));
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assign ZeroSgn = (PSgnM^ZSgnEffM)&~Underflow&~Mult ? FrmM[1:0] == 2'b10 : PSgnM;
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// is the result negitive
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// if p - z is the Sum negitive
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// if -p + z is the Sum positive
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// if -p - z then the Sum is negitive
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assign InfSgn = ZInfM ? ZSgnEffM : PSgnM;
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assign ResSgn = InfIn&FmaOp ? InfSgn : SumZero&FmaOp ? ZeroSgn : RoundSgn;
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endmodule |