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50 lines
1.9 KiB
Systemverilog
Executable File
50 lines
1.9 KiB
Systemverilog
Executable File
///////////////////////////////////////////
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// ram2p1rwbe_64x32.sv
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//
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// Written: james.stine@okstate.edu 28 January 2023
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// Modified:
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//
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// Purpose: RAM wrapper for instantiating RAM IP
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module ram2p1r1wbe_64x32(
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input logic CLKA,
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input logic CLKB,
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input logic CEBA,
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input logic CEBB,
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input logic WEBA,
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input logic WEBB,
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input logic [5:0] AA,
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input logic [5:0] AB,
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input logic [31:0] DA,
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input logic [31:0] DB,
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input logic [31:0] BWEBA,
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input logic [31:0] BWEBB,
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output logic [31:0] QA,
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output logic [31:0] QB
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);
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// replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor
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//generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
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// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
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TSDN28HPCPA64X32M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
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.AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
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endmodule
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