bbracker a6047697c3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main		2022-02-22 04:27:50 +00:00
..
common	Just needed to recompile - all good. Now removed uretM because N-mode is depricated	2022-02-15 19:48:49 +00:00
fp
sdc
testbench-coremark_bare.sv
testbench-f64.sv
testbench-fpga.sv	cache cleanup	2022-02-03 15:36:11 +00:00
testbench-linux.sv
testbench.sv	change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests	2022-02-22 03:46:08 +00:00
tests.vh	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-22 04:27:50 +00:00