mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 21:14:37 +00:00
| .. | ||
| berkeley-softfloat-3@3b70b5d814 | ||
| berkeley-testfloat-3@03c13d21db | ||
| branch-predictor-simulator@3e424e902f | ||
| coremark@f3e8f2e094 | ||
| cvw-arch-verif@6d658b7b42 | ||
| embench-iot@54fd9a0f10 | ||
| FreeRTOS-Kernel@17a46c252f | ||
| riscv-arch-test@3843c736e4 | ||
| riscv-dv@f0c570d112 | ||
| riscvISACOV@ac9fa2d386 | ||
| verilog-ethernet@c180b22ed5 | ||
| vivado-boards@e5f0728cd2 | ||
| README.md | ||
| sparse-checkout | ||
verilog-ethernet contains many ethernet devices. Wally's synthesizable RVVI interface only requires a small subset of these files. To do a sparse checkout of this repo copy sparse-checkout to cvw/.git/modules/addins/verilog-ethernet/info This will make the working directory only contain the necessary files.