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93 lines
4.0 KiB
Systemverilog
93 lines
4.0 KiB
Systemverilog
///////////////////////////////////////////
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// mul.sv
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//
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// Written: David_Harris@hmc.edu 16 February 2021
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// Modified:
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//
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// Purpose: Integer multiplication
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//
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// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.18)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module mul #(parameter XLEN) (
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input logic clk, reset,
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input logic StallM, FlushM,
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input logic [XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // source A and B from after Forwarding mux
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input logic [2:0] Funct3E, // type of multiply
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output logic [XLEN*2-1:0] ProdM // double-widthproduct
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);
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// Number systems
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// Let A' = sum(i=0, XLEN-2, A[i]*2^i)
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// Unsigned: A = A' + A[XLEN-1]*2^(XLEN-1)
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// Signed: A = A' - A[XLEN-1]*2^(XLEN-1)
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// Multiplication: A*B
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// Let P' = A' * B'
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// PA = (A' * B[XLEN-1])
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// PB = (B' * A[XLEN-1])
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// PP = A[XLEN-1] * B[XLEN-1]
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// Signed * Signed = P' + (-PA - PB)*2^(XLEN-1) + PP*2^(2XLEN-2)
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// Signed * Unsigned = P' + ( PA - PB)*2^(XLEN-1) - PP*2^(2XLEN-2)
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// Unsigned * Unsigned = P' + ( PA + PB)*2^(XLEN-1) + PP*2^(2XLEN-2)
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logic [XLEN-1:0] Aprime, Bprime; // lower bits of source A and B
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logic MULH, MULHSU; // type of multiply
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logic [XLEN-2:0] PA, PB; // product of msb and lsbs
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logic PP; // product of msbs
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logic [XLEN*2-1:0] PP1E, PP2E, PP3E, PP4E; // partial products
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logic [XLEN*2-1:0] PP1M, PP2M, PP3M, PP4M; // registered partial proudcts
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//////////////////////////////
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// Execute Stage: Compute partial products
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//////////////////////////////
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assign Aprime = {1'b0, ForwardedSrcAE[XLEN-2:0]};
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assign Bprime = {1'b0, ForwardedSrcBE[XLEN-2:0]};
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assign PP1E = Aprime * Bprime;
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assign PA = {(XLEN-1){ForwardedSrcAE[XLEN-1]}} & ForwardedSrcBE[XLEN-2:0];
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assign PB = {(XLEN-1){ForwardedSrcBE[XLEN-1]}} & ForwardedSrcAE[XLEN-2:0];
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assign PP = ForwardedSrcAE[XLEN-1] & ForwardedSrcBE[XLEN-1];
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// flavor of multiplication
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assign MULH = (Funct3E == 3'b001);
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assign MULHSU = (Funct3E == 3'b010);
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// Select partial products, handling signed multiplication
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assign PP2E = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(XLEN-1){1'b0}}};
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assign PP3E = {2'b00, (MULH) ? ~PB : PB, {(XLEN-1){1'b0}}};
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always_comb
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if (MULH) PP4E = {1'b1, PP, {(XLEN-3){1'b0}}, 1'b1, {(XLEN){1'b0}}};
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else if (MULHSU) PP4E = {1'b1, ~PP, {(XLEN-2){1'b0}}, 1'b1, {(XLEN-1){1'b0}}};
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else PP4E = {1'b0, PP, {(XLEN*2-2){1'b0}}};
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//////////////////////////////
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// Memory Stage: Sum partial proudcts
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//////////////////////////////
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flopenrc #(XLEN*2) PP1Reg(clk, reset, FlushM, ~StallM, PP1E, PP1M);
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flopenrc #(XLEN*2) PP2Reg(clk, reset, FlushM, ~StallM, PP2E, PP2M);
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flopenrc #(XLEN*2) PP3Reg(clk, reset, FlushM, ~StallM, PP3E, PP3M);
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flopenrc #(XLEN*2) PP4Reg(clk, reset, FlushM, ~StallM, PP4E, PP4M);
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// add up partial products; this multi-input add implies CSAs and a final CPA
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assign ProdM = PP1M + PP2M + PP3M + PP4M; //ForwardedSrcAE * ForwardedSrcBE;
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endmodule
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