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cvw/fpga/src
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Ross Thompson d33c966a42 Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock.
2023-10-10 17:46:12 -05:00
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axi_sdc_controller.v Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock. 2023-10-10 17:46:12 -05:00
fpgaTop.v Added help option to the flash-sd script. 2023-08-22 13:37:33 -05:00
fpgaTopArtyA7.v Fixed bugs in boot and new flash card merge. Works with arty a7 now. 2023-07-22 15:52:25 -05:00
wallypipelinedsocwrapper.sv Merge branch 'boot' into mergeBoot 2023-07-21 17:43:45 -05:00