Rose Thompson f1d9e18dee Modified fpga config to support two fpga boards with different amount of memory. ... Modified vcu108 constraints to better constrain the spi clock and in/out.		2024-08-29 16:12:58 -07:00
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axi_sdc_controller.v	Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock.	2023-10-10 17:46:12 -05:00
fpgaTop.sv	Modified fpga config to support two fpga boards with different amount of memory.	2024-08-29 16:12:58 -07:00
fpgaTopArtyA7.sv	Maybe improvements to fpga synthesis.	2024-08-23 13:00:22 -07:00
wallypipelinedsocwrapper.sv	Updated my name in multiple locations.	2024-08-21 10:50:39 -07:00