slmnemo e39f94b645 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main ... help		2021-12-08 14:09:58 -08:00
..
clint.sv	random lint cleanup	2021-10-23 11:24:36 -07:00
dtim.sv	Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict.	2021-12-08 15:50:15 -06:00
gpio.sv	Lint cleanup	2021-10-23 09:58:52 -07:00
plic.sv	Modified invalid plic reads to return 0 rather than deadbeaf.	2021-08-11 16:56:22 -05:00
subwordwrite.sv	Data memory bus integration	2021-02-07 23:21:55 -05:00
uart.sv	Removed .* from /wally-pipelined/src/uncore/uart.sv	2021-12-08 14:02:53 -08:00
uartPC16550D.sv	Fixed uart for FPGA config after merge. This still needs some work.	2021-11-29 16:07:54 -06:00
uncore.sv	Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict.	2021-12-08 15:50:15 -06:00