mirror of
https://github.com/openhwgroup/cvw
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150 lines
3.4 KiB
ArmAsm
150 lines
3.4 KiB
ArmAsm
///////////////////////////////////////////
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// priv.S
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//
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// Written: David_Harris@hmc.edu 23 March 2023
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//
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// Purpose: Test coverage for EBU
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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main:
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# switch to supervisor mode
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li a0, 1
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ecall
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# Test read to stimecmp fails when MCOUNTEREN_TM is not set
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li t1, -3
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csrw stimecmp, t1
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csrr t0, stimecmp
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# satp write with mstatus.TVM = 1
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bseti t0, zero, 20
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csrs mstatus, t0
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csrw satp, zero
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# STIMECMP from S mode
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li t0, 1
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ecall # enter S-mode
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csrw stimecmp, zero
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li t0, 3
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ecall # return to M-mode
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csrsi mcounteren, 2 # mcounteren_tm = 1
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li t0, 1
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ecall # supervisor mode again
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csrw stimecmp, zero
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li t0, 3
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ecall # machine mode again
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# switch to supervisor mode
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li a0, 1
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ecall
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# Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs
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li t0, 0
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csrw stval, t0
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csrw scause, t0
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csrw sepc, t0
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csrw stimecmp, t0
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csrw scounteren, zero
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csrw satp, zero
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# Switch to machine mode
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li a0, 3
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ecall
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# Write to MCOUNTINHIBIT CSR
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csrw mcountinhibit, t0
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# Testing the HPMCOUNTERM performance counter: writing
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# Base address is 2816 (MHPMCOUNTERBASE)
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# There are 32 HPMCOUNTER registers
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csrw 2816, t0
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csrw 2817, t0
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csrw 2818, t0
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csrw 2819, t0
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csrw 2820, t0
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csrw 2821, t0
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csrw 2822, t0
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csrw 2823, t0
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csrw 2824, t0
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csrw 2825, t0
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csrw 2826, t0
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csrw 2827, t0
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csrw 2828, t0
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csrw 2829, t0
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csrw 2830, t0
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csrw 2831, t0
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csrw 2832, t0
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csrw 2833, t0
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csrw 2834, t0
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csrw 2835, t0
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csrw 2836, t0
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csrw 2837, t0
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csrw 2838, t0
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csrw 2839, t0
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csrw 2840, t0
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csrw 2841, t0
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csrw 2842, t0
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csrw 2843, t0
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csrw 2844, t0
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csrw 2845, t0
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csrw 2846, t0
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csrw 2847, t0
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# Testing the HPMCOUNTERM performance counter: reading
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csrr t0, 2817
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# Test writes to pmp address registers
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csrw 951, t0
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csrw 952, t0
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csrw 953, t0
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csrw 954, t0
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csrw 955, t0
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csrw 956, t0
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csrw 957, t0
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csrw 958, t0
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# Testing writes to MTVAL, MCAUSE
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li t0, 0
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csrw mtval, t0
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csrw mcause, t0
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# set mstatus to enable floating point registers (mstatus.FS = 11)
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bseti t1, zero, 13
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csrs mstatus, t1
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bseti t1, zero, 14
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csrs mstatus, t1
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# Test writes to floating point CSRs
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csrw frm, t0
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csrw fflags, t0
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j done
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