mirror of
https://github.com/openhwgroup/cvw
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187 lines
9.3 KiB
Systemverilog
187 lines
9.3 KiB
Systemverilog
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`include "wally-config.vh"
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// `include "../../config/rv64icfd/wally-config.vh"
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// `define XLEN 64
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module fcvt (
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input logic XSgnE, // X's sign
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input logic [10:0] XExpE, // X's exponent
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input logic [52:0] XManE, // X's fraction
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input logic XZeroE, // is X zero
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input logic XNaNE, // is X NaN
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input logic XInfE, // is X infinity
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input logic XDenormE, // is X denormalized
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input logic [`XLEN-1:0] ForwardedSrcAE, // integer input
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input logic [2:0] FOpCtrlE, // chooses which instruction is done (full list below)
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input logic [2:0] FrmE, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic FmtE, // precision 1 = double 0 = single
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output logic [63:0] CvtResE, // convert final result
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output logic [4:0] CvtFlgE); // convert flags {invalid, divide by zero, overflow, underflow, inexact}
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logic ResSgn; // FP result's sign
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logic [10:0] ResExp,TmpExp; // FP result's exponent
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logic [51:0] ResFrac; // FP result's fraction
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logic [6:0] LZResP; // lz output
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logic [7:0] Bits; // how many bits are in the integer result
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logic [7:0] SubBits; // subtract these bits from the exponent (FP result)
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logic [64+51:0] ShiftedManTmp; // Shifted mantissa
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logic [64+51:0] ShiftVal; // value being shifted (to int - XMan, to FP - |integer input|)
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logic [64+1:0] ShiftedMan; // shifted mantissa truncated
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logic [64:0] RoundedTmp; // full size rounded result - in case of overfow
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logic [63:0] Rounded; // rounded result
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logic [12:0] ExpVal; // unbiased X exponent
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logic [12:0] ShiftCnt; // how much is the mantissa shifted
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logic [64-1:0] IntIn; // trimed integer input
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logic [64-1:0] PosInt; // absolute value of the integer input
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logic [63:0] CvtIntRes; // interger result from the fp -> int instructions
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logic [63:0] CvtFPRes; // floating point result from the int -> fp instructions
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logic Of, Uf; // did the integer result underflow or overflow
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logic Guard, Round, LSB, Sticky; // bits used to determine rounding
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logic Plus1,CalcPlus1; // do you add one for rounding
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logic SgnRes; // sign of the floating point result
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logic Res64, In64; // is the result or input 64 bits
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logic RoundMSB; // most significant bit of the fraction
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logic RoundSgn; // sign of the rounded result
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logic Invalid, Inexact; // flags
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// FOpCtrlE:
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// fcvt.w.s = 001
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// fcvt.wu.s = 011
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// fcvt.s.w = 000
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// fcvt.s.wu = 010
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// fcvt.l.s = 101
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// fcvt.lu.s = 111
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// fcvt.s.l = 100
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// fcvt.s.lu = 110
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// fcvt.w.d = 001
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// fcvt.wu.d = 011
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// fcvt.d.w = 000
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// fcvt.d.wu = 010
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// fcvt.l.d = 101
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// fcvt.lu.d = 111
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// fcvt.d.l = 100
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// fcvt.d.lu = 110
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// {long, unsigned, to int}
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// calculate signals based off the input and output's size
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assign Res64 = (FOpCtrlE[0]&FOpCtrlE[2]) | (FmtE&~FOpCtrlE[0]);
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assign In64 = (~FOpCtrlE[0]&FOpCtrlE[2]) | (FmtE&FOpCtrlE[0]);
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assign SubBits = In64 ? 8'd64 : 8'd32;
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assign Bits = Res64 ? 8'd64 : 8'd32;
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// calulate the unbiased exponent
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assign ExpVal = {1'b0,XExpE} - {1'b0, (11)'(`BIAS)} + {12'b0, XDenormE};
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////////////////////////////////////////////////////////
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// position the input in the most significant bits
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assign IntIn = FOpCtrlE[2] ? {ForwardedSrcAE, {64-`XLEN{1'b0}}} : {ForwardedSrcAE[31:0], 32'b0};
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// make the integer positive
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assign PosInt = IntIn[64-1]&~FOpCtrlE[1] ? -IntIn : IntIn;
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// determine the integer's sign
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assign ResSgn = ~FOpCtrlE[1]&IntIn[64-1];
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// Leading one detector
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logic [8:0] i;
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always_comb begin
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i = 0;
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while (~PosInt[64-1-i] & i < `XLEN) i = i+1; // search for leading one
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LZResP = i[5:0]+1; // compute shift count
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end
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// if no one was found set to zero otherwise calculate the exponent
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assign TmpExp = i==`XLEN ? 0 : FmtE ? 11'd1023 + {3'b0, SubBits} - {4'b0, LZResP} : 11'd127 + {3'b0, SubBits} - {4'b0, LZResP};
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////////////////////////////////////////////
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// select the shift value and amount based on operation (to fp or int)
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assign ShiftCnt = FOpCtrlE[0] ? ExpVal : {6'b0, LZResP};
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assign ShiftVal = FOpCtrlE[0] ? {{64-1{1'b0}}, XManE} : {PosInt, 52'b0};
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// if shift = -1 then shift one bit right for gaurd bit (right shifting twice never rounds)
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// if the shift is negitive add a bit for sticky bit calculation
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// otherwise shift left
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assign ShiftedManTmp = &ShiftCnt ? {{64{1'b0}}, XManE[52:1]} : ShiftCnt[12] ? {{64+51{1'b0}}, ~XZeroE} : ShiftVal << ShiftCnt;
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// truncate the shifted mantissa
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assign ShiftedMan = ShiftedManTmp[64+51:50];
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// calculate sticky bit
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// - take into account the possible right shift from before
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// - the sticky bit calculation covers three diffrent sizes depending on the opperation
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assign Sticky = |ShiftedManTmp[49:0] | &ShiftCnt&XManE[0] | (~FOpCtrlE[0]&|ShiftedManTmp[62:50]) | (~FOpCtrlE[0]&~FmtE&|ShiftedManTmp[91:63]);
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// determine guard, round, and least significant bit of the result
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assign Guard = FOpCtrlE[0] ? ShiftedMan[1] : FmtE ? ShiftedMan[13] : ShiftedMan[42];
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assign Round = FOpCtrlE[0] ? ShiftedMan[0] : FmtE ? ShiftedMan[12] : ShiftedMan[41];
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assign LSB = FOpCtrlE[0] ? ShiftedMan[2] : FmtE ? ShiftedMan[14] : ShiftedMan[43];
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always_comb begin//*** remove guard bit
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// Determine if you add 1
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case (FrmE)
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3'b000: CalcPlus1 = Guard & (Round | Sticky | (~Round&~Sticky&LSB));//round to nearest even
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3'b001: CalcPlus1 = 0;//round to zero
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3'b010: CalcPlus1 = (XSgnE&FOpCtrlE[0]) | (ResSgn&~FOpCtrlE[0]);//round down
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3'b011: CalcPlus1 = (~XSgnE&FOpCtrlE[0]) | (~ResSgn&~FOpCtrlE[0]);//round up
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3'b100: CalcPlus1 = Guard & (Round | Sticky | (~Round&~Sticky));//round to nearest max magnitude
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default: CalcPlus1 = 1'bx;
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endcase
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end
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// dont tound if the result is exact
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assign Plus1 = CalcPlus1 & (Guard|Round|Sticky)&~(XZeroE&FOpCtrlE[0]);
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// round the shifted mantissa
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assign RoundedTmp = ShiftedMan[64+1:2] + {64'b0, Plus1};
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assign {ResExp, ResFrac} = FmtE ? {TmpExp, ShiftedMan[64+1:14]} + {62'b0, Plus1} : {{TmpExp, ShiftedMan[64+1:43]} + {33'b0,Plus1}, 29'b0} ;
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// fit the rounded result into the appropriate size and take the 2's complement if needed
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assign Rounded = Res64 ? XSgnE&FOpCtrlE[0] ? -RoundedTmp[63:0] : RoundedTmp[63:0] :
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XSgnE ? {{32{1'b1}}, -RoundedTmp[31:0]} : {32'b0, RoundedTmp[31:0]};
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// extract the MSB and Sign for later use (will be used to determine underflow and overflow)
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assign RoundMSB = Res64 ? RoundedTmp[64] : RoundedTmp[32];
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assign RoundSgn = Res64 ? Rounded[63] : Rounded[31];
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// check if the result overflows
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assign Of = (~XSgnE&($signed(ShiftCnt) >= $signed({{5{Bits[7]}}, Bits}))) | (~XSgnE&RoundSgn&~FOpCtrlE[1]) | (RoundMSB&(ShiftCnt==({{5{Bits[7]}}, Bits}-1))) | (~XSgnE&XInfE) | XNaNE;
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// check if the result underflows (this calculation changes if the result is signed or unsigned)
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assign Uf = FOpCtrlE[1] ? XSgnE&~XZeroE | (XSgnE&XInfE) | (XSgnE&~XZeroE&(~ShiftCnt[12]|CalcPlus1)) | (ShiftCnt[12]&Plus1) : (XSgnE&XInfE) | (XSgnE&($signed(ShiftCnt) >= $signed({{5{Bits[7]}}, Bits}))) | (XSgnE&~RoundSgn&~ShiftCnt[12]); // assign CvtIntRes = (XSgnE | ShiftCnt[12]) ? {64{1'b0}} : (ShiftCnt >= 64) ? {64{1'b1}} : Rounded;
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// calculate the result's sign
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assign SgnRes = ~FOpCtrlE[2] & FOpCtrlE[0];
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// select the integer result
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assign CvtIntRes = Of ? FOpCtrlE[1] ? {64{1'b1}} : SgnRes ? {33'b0, {31{1'b1}}}: {1'b0, {63{1'b1}}} :
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Uf ? FOpCtrlE[1] ? {63'b0, Plus1&~XSgnE} : SgnRes ? {{33{1'b1}}, 31'b0} : {1'b1, 63'b0} :
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|RoundedTmp ? Rounded[64-1:0] : 64'b0;
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// select the floating point result
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assign CvtFPRes = FmtE ? {ResSgn, ResExp, ResFrac} : {{32{1'b1}}, ResSgn, ResExp[7:0], ResFrac[51:29]};
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// select the result
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assign CvtResE = FOpCtrlE[0] ? CvtIntRes : CvtFPRes;
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// calculate the flags
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// - only set invalid flag for out-of-range vales
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// - set inexact if in representable range and not exact
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if(`IEEE754) begin // checks before rounding
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assign Invalid = (Of | Uf)&FOpCtrlE[0];
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assign Inexact = (Guard|Round|Sticky)&~(&FOpCtrlE[1:0]&(XSgnE|Of))&~((Of|Uf)&~FOpCtrlE[1]&FOpCtrlE[0]);
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assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact};
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end else begin // RISC-V checks if the result is in range after rounding
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assign Invalid = (Of | Uf)&FOpCtrlE[0];
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assign Inexact = (Guard|Round|Sticky)&~(&FOpCtrlE[1:0]&((XSgnE&~(ShiftCnt[12]&~Plus1))|Of))&~((Of|Uf)&~FOpCtrlE[1]&FOpCtrlE[0]);
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assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact};
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end
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endmodule // fpadd
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