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https://github.com/openhwgroup/cvw
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86 lines
3.0 KiB
Verilog
86 lines
3.0 KiB
Verilog
///////////////////////////////////////////////////////////////////////////////
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// Block Name: flag.v
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// Author: David Harris
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// Date: 12/6/1995
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//
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// Block Description:
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// This block generates the flags: invalid, overflow, underflow, inexact.
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/////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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module flag(xnan, ynan, znan, xinf, yinf, zinf, prodof, sumof, sumuf,
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psign, zsign, xzero, yzero, v[1:0],
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inf, nan, invalid, overflow, underflow, inexact);
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/////////////////////////////////////////////////////////////////////////////
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input xnan; // X is NaN
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input ynan; // Y is NaN
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input znan; // Z is NaN
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input xinf; // X is Inf
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input yinf; // Y is Inf
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input zinf; // Z is Inf
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input prodof; // X*Y overflows exponent
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input sumof; // X*Y + z underflows exponent
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input sumuf; // X*Y + z underflows exponent
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input psign; // Sign of product
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input zsign; // Sign of z
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input xzero; // x = 0
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input yzero; // y = 0
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input [1:0] v; // R and S bits of result
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output inf; // Some source is Inf
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output nan; // Some source is NaN
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output invalid; // Result is invalid
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output overflow; // Result overflowed
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output underflow; // Result underflowed
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output inexact; // Result is not an exact number
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// Internal nodes
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wire prodinf; // X*Y larger than max possible
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wire suminf; // X*Y+Z larger than max possible
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// If any input is NaN, propagate the NaN
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assign nan = xnan || ynan || znan;
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// Same with infinity (inf - inf and O * inf don't propagate inf
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// but it's ok becaue illegal op takes higher precidence)
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assign inf= xinf || yinf || zinf;
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// Generate infinity checks
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assign prodinf = prodof && ~xnan && ~ynan;
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assign suminf = sumof && ~xnan && ~ynan && ~znan;
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// Set invalid flag for following cases:
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// 1) Inf - Inf
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// 2) 0 * Inf
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// 3) Output = NaN (this is not part of the IEEE spec, only 486 proj)
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assign invalid = (xinf || yinf || prodinf) && zinf && (psign ^ zsign) ||
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xzero && yinf || yzero && xinf ||
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nan;
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// Set the overflow flag for the following cases:
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// 1) Rounded multiply result would be out of bounds
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// 2) Rounded add result would be out of bounds
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assign overflow = suminf && ~inf;
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// Set the underflow flag for the following cases:
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// 1) Any input is denormalized
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// 2) Output would be denormalized or smaller
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assign underflow = (sumuf && ~inf && ~prodinf && ~nan);
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// Set the inexact flag for the following cases:
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// 1) Multiplication inexact
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// 2) Addition inexact
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// One of these cases occurred if the R or S bit is set
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assign inexact = (v[0] || v[1] || suminf) && ~(inf || nan);
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endmodule
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