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11 lines
246 B
Systemverilog
11 lines
246 B
Systemverilog
module logging(
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input logic clk, reset,
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input logic [31:0] HADDR,
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input logic [1:0] HTRANS);
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always @(posedge clk)
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if (HTRANS != 2'b00 && HADDR == 0)
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$display("%t Warning: access to memory address 0\n", $realtime);
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endmodule
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