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50 lines
2.0 KiB
Plaintext
Executable File
50 lines
2.0 KiB
Plaintext
Executable File
Connect JTAG adapter (SiPEED) to FPGA (Arty-A7)
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Using Pmod JA (side closest to ethernet port)
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Connect 5 jumpers on the top row beginning with GND
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The order of the wires matches the order of the USB Adapter
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GND TDI TMS TDO TCK
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(see jtag_pinout.jpg)
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To debug Wally using OpenOCD:
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1. Select correct jtag adapter
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If using "SiPEED" adapters, openocd.cfg already contains the correct adapter ftdi
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with vid_pid 0x0403 0x6010
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If there are multiple ft2232 chips connected to the same system (ex: Arty-A7),
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you will need to tell OpenOCD which one to use.
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On linux:
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list your USB devices usign the command: "lsusb -t"
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example output:
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/: Bus 001.Port 001: Dev 001, Class=root_hub, Driver=xhci_hcd/10p, 480M
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|__ Port 003: Dev 002, If 0, Class=Vendor Specific Class, Driver=usbfs, 480M
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|__ Port 003: Dev 002, If 1, Class=Vendor Specific Class, Driver=ftdi_sio, 480M
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|__ Port 004: Dev 004, If 0, Class=Vendor Specific Class, Driver=usbfs, 12M
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|__ Port 004: Dev 004, If 1, Class=Vendor Specific Class, Driver=ftdi_sio, 12M <- This is my JTAG adapter
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In the openOCD config, add the line: "adapter usb location 1-4"
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where the numbers 1-4 correspond to <bus_num>-<port_num>
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2. Run openocd
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run openocd using the command "openocd -f openocd.cfg"
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where openocd.cfg is the path of the config file
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If everything is working corretly, OpenOCD should start without any errors and begin listening for telnet and gdb connections
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connect to openocd via telnet (telnet 127.0.0.1 4444) to send commands via the command line
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3. read and write to the DMI bus
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the riscv debug module can be controlled by writing to various registers via the DMI.
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We can access these registers using the two commands:
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riscv dmi_read <address>
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riscv dmi_write <address> <value>
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4. Initialize the DM
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The debug module starts in an inactive state. In this state, it will not respond to any commands
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To activate it, write 0x1 to the DMCONTROL register (0x10):
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"riscv dmi_write 0x10 0x1"
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Now you should have full control over the debug module.
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