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97 lines
3.0 KiB
Systemverilog
97 lines
3.0 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtstage4.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtstage4 (
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input logic [`DIVb-1:0] D,
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input logic [`DIVb+3:0] DBar, D2, DBar2,
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input logic [`DIVb:0] U, UM,
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input logic [`DIVb+3:0] WS, WC,
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input logic [`DIVb+1:0] C,
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input logic SqrtE, j1,
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output logic [`DIVb+1:0] CNext,
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output logic un,
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output logic [`DIVb:0] UNext, UMNext,
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output logic [`DIVb+3:0] WSNext, WCNext
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);
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logic [`DIVb+3:0] Dsel;
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logic [3:0] udigit;
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logic [`DIVb+3:0] F;
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logic [`DIVb+3:0] AddIn;
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logic [4:0] Smsbs;
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logic [2:0] Dmsbs;
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logic [7:0] WCmsbs, WSmsbs;
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logic CarryIn;
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logic [`DIVb+3:0] WSA, WCA;
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// Digit Selection logic
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// u encoding:
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// 1000 = +2
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// 0100 = +1
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// 0000 = 0
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// 0010 = -1
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// 0001 = -2
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assign Smsbs = U[`DIVb:`DIVb-4];
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assign Dmsbs = D[`DIVb-1:`DIVb-3];
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assign WCmsbs = WC[`DIVb+3:`DIVb-4];
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assign WSmsbs = WS[`DIVb+3:`DIVb-4];
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fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit);
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assign un = 1'b0; // unused for radix 4
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// F generation logic
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fdivsqrtfgen4 fgen4(.udigit, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
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// Divisor multiple logic
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always_comb
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case (udigit)
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4'b1000: Dsel = DBar2;
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4'b0100: Dsel = DBar;
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4'b0000: Dsel = '0;
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4'b0010: Dsel = {3'b0, 1'b1, D};
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4'b0001: Dsel = D2;
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default: Dsel = 'x;
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endcase
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// Residual Update
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// {WS, WC}}Next = (WS + WC - qD or F) << 2
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assign AddIn = SqrtE ? F : Dsel;
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assign CarryIn = ~SqrtE & (udigit[3] | udigit[2]); // +1 for 2's complement of -D and -2D
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csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA);
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assign WSNext = WSA << 2;
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assign WCNext = WCA << 2;
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// Shift thermometer code C
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assign CNext = {2'b11, C[`DIVb+1:2]};
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// On-the-fly converter to accumulate result
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fdivsqrtuotfc4 fdivsqrtuotfc4(.udigit, .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext);
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endmodule
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