Ross Thompson 76bba541a7 Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.		2021-10-24 21:21:49 -05:00
..
bin	Added testbench-arch for riscv-arch-test suite	2021-09-08 15:59:40 -04:00
config	removed reduntant definitions for FPU in MISA.	2021-10-22 15:18:25 -05:00
fpu-testfloat/FMA/tbgen	FMA matches diagram and lint warnings fixed	2021-10-09 17:38:10 -07:00
linux-testgen	update linker scripts to look for vmlinux files	2021-10-06 16:55:38 -04:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	or actually needed to reduce expectations of buildroot	2021-10-24 06:59:34 -07:00
src	Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.	2021-10-24 21:21:49 -05:00
srt	moved coemark and testsBP to tests	2021-10-20 09:10:06 -07:00
testbench	add W stage signals to linux testbench	2021-10-23 14:00:53 -07:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00