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47 lines
1.7 KiB
Systemverilog
47 lines
1.7 KiB
Systemverilog
///////////////////////////////////////////
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// priorityaomux.sv
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//
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// Written: Rose Thompson ross1728@gmail.com
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// Created: 24 January 2024
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// Modified: 24 January 2024
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//
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// Purpose: priority AND-OR MUX.
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//
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// Documentation:
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module priorityaomux #(parameter ROWS = 8, COLS = 64) (
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input logic [ROWS-1:0] Sel,
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input var logic [COLS-1:0] A [ROWS-1:0],
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output logic [COLS-1:0] Y,
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output logic [ROWS-1:0] SelPriority);
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logic [COLS-1:0] AMasked [ROWS-1:0];
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genvar index;
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priorityonehot #(ROWS) priorityonehot(Sel, SelPriority);
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for(index = 0; index < ROWS; index = index + 1) begin
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assign AMasked[index] = SelPriority[index] ? A[index] : '0;
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end
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or_rows #(ROWS, COLS) or_rows(AMasked, Y);
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endmodule
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