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https://github.com/openhwgroup/cvw
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44 lines
679 B
Systemverilog
44 lines
679 B
Systemverilog
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// Black cell
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module black(gout, pout, gin, pin);
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input [1:0] gin, pin;
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output gout, pout;
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assign pout=pin[1]&pin[0];
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assign gout=gin[1]|(pin[1]&gin[0]);
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endmodule // black
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// Grey cell
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module grey(gout, gin, pin);
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input[1:0] gin;
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input pin;
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output gout;
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assign gout=gin[1]|(pin&gin[0]);
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endmodule // grey
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// reduced Black cell
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module rblk(hout, iout, gin, pin);
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input [1:0] gin, pin;
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output hout, iout;
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assign iout=pin[1]&pin[0];
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assign hout=gin[1]|gin[0];
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endmodule // rblk
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// reduced Grey cell
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module rgry(hout, gin);
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input[1:0] gin;
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output hout;
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assign hout=gin[1]|gin[0];
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endmodule // rgry
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