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66 lines
2.6 KiB
Systemverilog
66 lines
2.6 KiB
Systemverilog
////////////////////////////////////////////////////////////////////////////////
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//
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// Block Name: add.v
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// Author: David Harris
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// Date: 11/12/1995
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//
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// Block Description:
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// This block performs the addition of the product and addend. It also
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// contains logic necessary to adjust the signs for effective subtracts
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// and negative results.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module add(rM, sM, tM, sum,
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negsum, invz, selsum1, negsum0, negsum1, killprodM);
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////////////////////////////////////////////////////////////////////////////////
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input logic [105:0] rM; // partial product 1
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input logic [105:0] sM; // partial product 2
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input logic [163:0] tM; // aligned addend
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input logic invz; // invert addend
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input logic selsum1; // select +1 mode of compound adder
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input logic killprodM; // z >> product
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input logic negsum; // Negate sum
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output logic [163:0] sum; // sum
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output logic negsum0; // sum was negative in +0 mode
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output logic negsum1; // sum was negative in +1 mode
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// Internal nodes
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wire [105:0] r2; // partial product possibly zeroed out
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wire [105:0] s2; // partial product possibly zeroed out
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wire [164:0] t2; // addend after inversion if necessary
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wire [164:0] sum0; // sum of compound adder +0 mode
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wire [164:0] sum1; // sum of compound adder +1 mode
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wire [163:0] prodshifted; // sum of compound adder +1 mode
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wire [164:0] tmp; // sum of compound adder +1 mode
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// Invert addend if z'sM sign is diffrent from the product'sM sign
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assign t2 = invz ? ~{1'b0,tM} : {1'b0,tM};
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// Zero out product if Z >> product or product really should be
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assign r2 = killprodM ? 106'b0 : rM;
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assign s2 = killprodM ? 106'b0 : sM;
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//***replace this with a more structural cpa that synthisises better
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// Compound adder
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// Consists of 3:2 CSA followed by long compound CPA
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//assign prodshifted = killprodM ? 0 : {56'b0, r2+s2, 2'b0};
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//assign tmp = ({{57{r2[105]}},r2, 2'b0} + {{57{s2[105]}},s2, 2'b0});
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assign sum0 = t2 + 164'b0 + {57'b0, r2+s2, 2'b0};
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assign sum1 = t2 + 164'b1 + {57'b0, r2+s2, 2'b0}; // +1 from invert of z above
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// Check sign bits in +0/1 modes
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assign negsum0 = sum0[164];
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assign negsum1 = sum1[164];
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// Mux proper result (+Oil mode and inversion) using 4:1 mux
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//assign sumzero = |sum;
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assign sum = selsum1 ? (negsum ? -sum1[163:0] : sum1[163:0]) : (negsum ? -sum0[163:0] : sum0[163:0]);
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endmodule
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