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								adderparts.sv
							
						
					
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							rename adder in fpu for synthesis
						
					
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				2021-10-08 17:47:54 -05:00 | 
			
		
			
			
			
			
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								cla12.sv
							
						
					
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							fpu cleanup
						
					
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				2021-07-24 14:59:57 -04:00 | 
			
		
			
			
			
			
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								cla52.sv
							
						
					
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							fpu cleanup
						
					
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				2021-07-24 14:59:57 -04:00 | 
			
		
			
			
			
			
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								cla64.sv
							
						
					
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							fpu cleanup
						
					
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				2021-07-24 14:59:57 -04:00 | 
			
		
			
			
			
			
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								convert_inputs_div.sv
							
						
					
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							fpu cleanup
						
					
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				2021-07-24 14:59:57 -04:00 | 
			
		
			
			
			
			
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								convert_inputs.sv
							
						
					
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							Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat
						
					
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				2021-10-06 08:26:09 -05:00 | 
			
		
			
			
			
			
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								cvtfp.sv
							
						
					
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							cvtfp module documented
						
					
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				2021-10-14 15:25:31 -07:00 | 
			
		
			
			
			
			
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								divconv_pipe.sv
							
						
					
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							Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.
						
					
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				2021-10-20 12:00:41 -05:00 | 
			
		
			
			
			
			
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								divconv.sv
							
						
					
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							Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.
						
					
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				2021-10-20 12:00:41 -05:00 | 
			
		
			
			
			
			
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								exception_div.sv
							
						
					
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							Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat
						
					
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				2021-10-06 08:26:09 -05:00 | 
			
		
			
			
			
			
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								exception.sv
							
						
					
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							all fpu units use the unpacking unit
						
					
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				2021-07-28 23:49:21 -04:00 | 
			
		
			
			
			
			
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								faddcvt.sv
							
						
					
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							LZA added to FMA and attemting a merged FMA and adder in synthesis
						
					
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				2021-08-10 13:57:16 -04:00 | 
			
		
			
			
			
			
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								fclassify.sv
							
						
					
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							fpu cleanup
						
					
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				2021-07-24 14:59:57 -04:00 | 
			
		
			
			
			
			
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								fcmp.sv
							
						
					
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							fpu unpacking unit created
						
					
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				2021-07-14 17:56:49 -04:00 | 
			
		
			
			
			
			
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								fctrl.sv
							
						
					
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							lint warnings fixed
						
					
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				2021-10-12 09:45:02 -07:00 | 
			
		
			
			
			
			
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								fcvt.sv
							
						
					
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							lint warnings fixed
						
					
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				2021-10-12 09:45:02 -07:00 | 
			
		
			
			
			
			
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								fhazard.sv
							
						
					
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							lint warnings fixed
						
					
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				2021-10-12 09:45:02 -07:00 | 
			
		
			
			
			
			
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								fma.sv
							
						
					
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							lint warnings fixed
						
					
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				2021-10-12 09:45:02 -07:00 | 
			
		
			
			
			
			
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								fpdiv_pipe.sv
							
						
					
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							Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.
						
					
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				2021-10-20 12:00:41 -05:00 | 
			
		
			
			
			
			
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								fpdiv.sv
							
						
					
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							Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.
						
					
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				2021-10-20 12:00:41 -05:00 | 
			
		
			
			
			
			
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								fpu.sv
							
						
					
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							Clean up some signals - beautification onging
						
					
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				2021-10-14 17:12:00 -05:00 | 
			
		
			
			
			
			
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								fpudivsqrtrecur.sv
							
						
					
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							Modified rxfull determination in UART, started division
						
					
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				2021-09-12 20:00:24 -04:00 | 
			
		
			
			
			
			
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								fpudivsqrtrecurcore.sv
							
						
					
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							Modified rxfull determination in UART, started division
						
					
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				2021-09-12 20:00:24 -04:00 | 
			
		
			
			
			
			
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								fregfile.sv
							
						
					
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							Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat
						
					
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				2021-10-06 08:26:09 -05:00 | 
			
		
			
			
			
			
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								fsgn.sv
							
						
					
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							fpu cleanup
						
					
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				2021-07-24 14:59:57 -04:00 | 
			
		
			
			
			
			
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								fsm_fpdiv_pipe.sv
							
						
					
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							Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.
						
					
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				2021-10-20 12:00:41 -05:00 | 
			
		
			
			
			
			
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								fsm_fpdiv.sv
							
						
					
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							Clean up some signals - beautification onging
						
					
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				2021-10-14 17:12:00 -05:00 | 
			
		
			
			
			
			
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								lzd_denorm.sv
							
						
					
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							fpu cleanup
						
					
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				2021-07-24 14:59:57 -04:00 | 
			
		
			
			
			
			
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								rounder_denorm.sv
							
						
					
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							all fpu units use the unpacking unit
						
					
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				2021-07-28 23:49:21 -04:00 | 
			
		
			
			
			
			
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								rounder_div.sv
							
						
					
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							Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.
						
					
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				2021-10-20 12:00:41 -05:00 | 
			
		
			
			
			
			
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								sbtm_a0.sv
							
						
					
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							Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat
						
					
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				2021-10-06 08:26:09 -05:00 | 
			
		
			
			
			
			
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								sbtm_a1.sv
							
						
					
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							Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat
						
					
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				2021-10-06 08:26:09 -05:00 | 
			
		
			
			
			
			
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								sbtm_a2.sv
							
						
					
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							Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat
						
					
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				2021-10-06 08:26:09 -05:00 | 
			
		
			
			
			
			
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								sbtm_a3.sv
							
						
					
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							Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat
						
					
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				2021-10-06 08:26:09 -05:00 | 
			
		
			
			
			
			
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								sbtm_div.sv
							
						
					
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							Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat
						
					
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				2021-10-06 08:26:09 -05:00 | 
			
		
			
			
			
			
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								sbtm_sqrt.sv
							
						
					
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							Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat
						
					
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				2021-10-06 08:26:09 -05:00 | 
			
		
			
			
			
			
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								shifter_denorm.sv
							
						
					
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							fpu cleanup
						
					
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				2021-07-24 14:59:57 -04:00 | 
			
		
			
			
			
			
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								unpacking.sv
							
						
					
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							lint warnings fixed
						
					
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				2021-10-12 09:45:02 -07:00 |