Ross Thompson 38edbde966 Renamed RW signals through the caches, bus interfaces, and IFU/LSU. ... CPU to $ is called LSURWM or IFURWF. CPU to Bus is called BusRW $ to Bus is called CacheBusRW.		2022-09-23 11:46:53 -05:00
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cache.sv	Renamed RW signals through the caches, bus interfaces, and IFU/LSU.	2022-09-23 11:46:53 -05:00
cachefsm.sv	Renamed RW signals through the caches, bus interfaces, and IFU/LSU.	2022-09-23 11:46:53 -05:00
cachereplacementpolicy.sv	Fixed an issue with direct map cache's nextway logic.	2022-07-06 18:34:30 -05:00
cacheway.sv	Renamed RW signals through the caches, bus interfaces, and IFU/LSU.	2022-09-23 11:46:53 -05:00
subcachelineread.sv	Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.	2022-08-01 21:08:14 -05:00
ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v	Update SRAM to /proj/wally	2022-07-08 08:09:55 -05:00