mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 13:04:28 +00:00
297 lines
16 KiB
Tcl
297 lines
16 KiB
Tcl
# The main clocks are all autogenerated by the Xilinx IP
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# clk_out3_xlnx_mmcm is the 20Mhz clock from the mmcm used to drive wally and the AHB Bus.
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# mmcm_clkout0 is the clock output of the DDR3 memory interface / 4.
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# This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP.
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#create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
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create_generated_clock -name SPISDCClock -source [get_pins mmcm/clk_out3] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICLK]
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##### clock #####
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set_property PACKAGE_PIN E3 [get_ports default_100mhz_clk]
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set_property IOSTANDARD LVCMOS33 [get_ports default_100mhz_clk]
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##### RVVI Ethernet ####
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# taken from https://github.com/alexforencich/verilog-ethernet/blob/master/example/Arty/fpga/fpga.xdc
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set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk]
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set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}]
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set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}]
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set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}]
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set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}]
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set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv]
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set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er]
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set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk]
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set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}]
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set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}]
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set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}]
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set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}]
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set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en]
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set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col]
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set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs]
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set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk]
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set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
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create_clock -period 40.000 -name phy_rx_clk [get_ports phy_rx_clk]
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create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk]
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set_false_path -to [get_ports {phy_ref_clk phy_reset_n}]
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set_output_delay 0.000 [get_ports {phy_ref_clk phy_reset_n}]
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##### GPI ####
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set_property PACKAGE_PIN A8 [get_ports {GPI[0]}]
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set_property PACKAGE_PIN C9 [get_ports {GPI[1]}]
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set_property PACKAGE_PIN B9 [get_ports {GPI[2]}]
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set_property PACKAGE_PIN B8 [get_ports {GPI[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPI[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPI[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPI[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPI[0]}]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPI[*]}]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPI[*]}]
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set_max_delay -from [get_ports {GPI[*]}] 20.000
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##### GPO ####
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set_property PACKAGE_PIN G6 [get_ports {GPO[0]}]
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set_property PACKAGE_PIN F6 [get_ports {GPO[1]}]
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set_property PACKAGE_PIN E1 [get_ports {GPO[2]}]
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set_property PACKAGE_PIN G3 [get_ports {GPO[4]}]
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set_property PACKAGE_PIN J4 [get_ports {GPO[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPO[4]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPO[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPO[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPO[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPO[0]}]
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set_max_delay -to [get_ports {GPO[*]}] 20.000
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set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
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set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}]
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##### UART #####
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# *** IOSTANDARD is probably wrong
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set_property PACKAGE_PIN A9 [get_ports UARTSin]
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set_property PACKAGE_PIN D10 [get_ports UARTSout]
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set_max_delay -from [get_ports UARTSin] 20.000
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set_max_delay -to [get_ports UARTSout] 20.000
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set_property IOSTANDARD LVCMOS33 [get_ports UARTSin]
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set_property IOSTANDARD LVCMOS33 [get_ports UARTSout]
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set_property DRIVE 4 [get_ports UARTSout]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSin]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSin]
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set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
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set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSout]
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##### reset #####
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#************** reset is inverted
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports resetn]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports resetn]
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set_max_delay -from [get_ports resetn] 20.000
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set_false_path -from [get_ports resetn]
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set_property PACKAGE_PIN C2 [get_ports resetn]
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set_property IOSTANDARD LVCMOS33 [get_ports resetn]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports south_reset]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports south_reset]
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set_max_delay -from [get_ports south_reset] 20.000
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set_false_path -from [get_ports south_reset]
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set_property PACKAGE_PIN D9 [get_ports south_reset]
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set_property IOSTANDARD LVCMOS33 [get_ports south_reset]
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##### SD Card I/O #####
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#***** may have to switch to Pmod JB or JC.
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#set_property PACKAGE_PIN D4 [get_ports {SDCDat[3]}]
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#set_property PACKAGE_PIN D2 [get_ports {SDCDat[2]}]
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#set_property PACKAGE_PIN E2 [get_ports {SDCDat[1]}]
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#set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}]
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#set_property PACKAGE_PIN F3 [get_ports SDCCLK]
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#set_property PACKAGE_PIN D3 [get_ports {SDCCmd}]
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#set_property PACKAGE_PIN H2 [get_ports {SDCCD}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
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#set_property IOSTANDARD LVCMOS33 [get_ports {SDCCmd}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {SDCCD}]
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#set_property PULLUP true [get_ports {SDCDat[3]}]
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#set_property PULLUP true [get_ports {SDCDat[2]}]
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#set_property PULLUP true [get_ports {SDCDat[1]}]
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#set_property PULLUP true [get_ports {SDCDat[0]}]
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#set_property PULLUP true [get_ports {SDCCmd}]
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#set_property PULLUP true [get_ports {SDCCD}]
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# SDCDat[3]
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set_property PACKAGE_PIN D4 [get_ports SDCCS]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCS]
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set_property PULLTYPE PULLUP [get_ports SDCCS]
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# set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}]
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# set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}]
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# SDCDat[0]
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set_property PACKAGE_PIN F4 [get_ports SDCIn]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCIn]
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set_property PULLTYPE PULLUP [get_ports SDCIn]
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set_property PACKAGE_PIN F3 [get_ports SDCCLK]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
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set_property PULLTYPE PULLUP [get_ports SDCCLK]
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set_property PACKAGE_PIN D3 [get_ports SDCCmd]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCmd]
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set_property PULLTYPE PULLUP [get_ports SDCCmd]
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set_property PACKAGE_PIN H2 [get_ports SDCCD]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCD]
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set_property PULLTYPE PULLUP [get_ports SDCCD]
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set_property PACKAGE_PIN G2 [get_ports SDCWP]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCWP]
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set_property PULLTYPE PULLUP [get_ports SDCWP]
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set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
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set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
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set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}]
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set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}]
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set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK]
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#set_multicycle_path -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10
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set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000
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# *********************************
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#set_property DCI_CASCADE {64} [get_iobanks 65]
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#set_property INTERNAL_VREF 0.9 [get_iobanks 65]
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# ddr3
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
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set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]]
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set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_cke[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_odt[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}]
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set_property PACKAGE_PIN K5 [get_ports ddr3_dq[0]]
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set_property PACKAGE_PIN L3 [get_ports ddr3_dq[1]]
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set_property PACKAGE_PIN K3 [get_ports ddr3_dq[2]]
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set_property PACKAGE_PIN L6 [get_ports ddr3_dq[3]]
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set_property PACKAGE_PIN M3 [get_ports ddr3_dq[4]]
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set_property PACKAGE_PIN M1 [get_ports ddr3_dq[5]]
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set_property PACKAGE_PIN L4 [get_ports ddr3_dq[6]]
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set_property PACKAGE_PIN M2 [get_ports ddr3_dq[7]]
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set_property PACKAGE_PIN V4 [get_ports ddr3_dq[8]]
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set_property PACKAGE_PIN T5 [get_ports ddr3_dq[9]]
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set_property PACKAGE_PIN U4 [get_ports ddr3_dq[10]]
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set_property PACKAGE_PIN V5 [get_ports ddr3_dq[11]]
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set_property PACKAGE_PIN V1 [get_ports ddr3_dq[12]]
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set_property PACKAGE_PIN T3 [get_ports ddr3_dq[13]]
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set_property PACKAGE_PIN U3 [get_ports ddr3_dq[14]]
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set_property PACKAGE_PIN R3 [get_ports ddr3_dq[15]]
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set_property PACKAGE_PIN L1 [get_ports ddr3_dm[0]]
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set_property PACKAGE_PIN U1 [get_ports ddr3_dm[1]]
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set_property PACKAGE_PIN N2 [get_ports ddr3_dqs_p[0]]
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set_property PACKAGE_PIN N1 [get_ports ddr3_dqs_n[0]]
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set_property PACKAGE_PIN U2 [get_ports ddr3_dqs_p[1]]
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set_property PACKAGE_PIN V2 [get_ports ddr3_dqs_n[1]]
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set_property PACKAGE_PIN T8 [get_ports ddr3_addr[13]]
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set_property PACKAGE_PIN T6 [get_ports ddr3_addr[12]]
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set_property PACKAGE_PIN U6 [get_ports ddr3_addr[11]]
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set_property PACKAGE_PIN R6 [get_ports ddr3_addr[10]]
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set_property PACKAGE_PIN V7 [get_ports ddr3_addr[9]]
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set_property PACKAGE_PIN R8 [get_ports ddr3_addr[8]]
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set_property PACKAGE_PIN U7 [get_ports ddr3_addr[7]]
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set_property PACKAGE_PIN V6 [get_ports ddr3_addr[6]]
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set_property PACKAGE_PIN R7 [get_ports ddr3_addr[5]]
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set_property PACKAGE_PIN N6 [get_ports ddr3_addr[4]]
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set_property PACKAGE_PIN T1 [get_ports ddr3_addr[3]]
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set_property PACKAGE_PIN N4 [get_ports ddr3_addr[2]]
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set_property PACKAGE_PIN M6 [get_ports ddr3_addr[1]]
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set_property PACKAGE_PIN R2 [get_ports ddr3_addr[0]]
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set_property PACKAGE_PIN P2 [get_ports ddr3_ba[2]]
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set_property PACKAGE_PIN P4 [get_ports ddr3_ba[1]]
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set_property PACKAGE_PIN R1 [get_ports ddr3_ba[0]]
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set_property PACKAGE_PIN U9 [get_ports ddr3_ck_p[0]]
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set_property PACKAGE_PIN V9 [get_ports ddr3_ck_n[0]]
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set_property PACKAGE_PIN P3 [get_ports ddr3_ras_n]
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set_property PACKAGE_PIN M4 [get_ports ddr3_cas_n]
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set_property PACKAGE_PIN P5 [get_ports ddr3_we_n]
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set_property PACKAGE_PIN K6 [get_ports ddr3_reset_n]
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set_property PACKAGE_PIN N5 [get_ports ddr3_cke[0]]
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set_property PACKAGE_PIN R5 [get_ports ddr3_odt[0]]
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set_property PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
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#create_clock -period 50.000 -name VIRTUAL_clk_out3_mmcm -waveform {0.000 25.000}
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#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports {GPI[*]}]
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#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPI[*]}]
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#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCCD]
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#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCD]
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#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCIn]
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#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCIn]
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#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCWP]
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#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCWP]
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#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports UARTSin]
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#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSin]
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#create_clock -period 12.000 -name VIRTUAL_clk_pll_i -waveform {0.000 6.000}
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#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
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#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPO[*]}]
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#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCLK]
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#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 0.000 [get_ports SDCCLK]
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#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCS]
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#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCS]
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#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCmd]
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#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCmd]
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#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
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#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSout]
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#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -min -add_delay 0.000 [get_ports ddr3_reset_n]
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#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -max -add_delay 80.000 [get_ports ddr3_reset_n]
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