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cvw/synthDC
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Madeleine Masser-Frye 6ece31183c Fixed config file writing for synthesis (#29) 
* Fixed writing config files for synth sweeps

* cleaned up comments
2023-01-26 06:58:15 +02:00
..
ppa explanations and modifications for general ppa use 2022-07-09 03:24:47 +00:00
scripts Rolled back synth scripts to fff91ae commit before Madeleine's modifications to write config files; the modified version is failing right away with trouble copying configs 2022-08-24 00:09:16 +00:00
.synopsys_dc.setup Rolled back synth scripts to fff91ae commit before Madeleine's modifications to write config files; the modified version is failing right away with trouble copying configs 2022-08-24 00:09:16 +00:00
extractSummary.py Fixed config file writing for synthesis (#29) 2023-01-26 06:58:15 +02:00
Makefile Fixed config file writing for synthesis (#29) 2023-01-26 06:58:15 +02:00
README.md
wallySynth.py Fixed config file writing for synthesis (#29) 2023-01-26 06:58:15 +02:00

README.md

Synthesis for RISC-V Microprocessor System-on-Chip Design

This subdirectory contains synthesis scripts for use with Synopsys (snps) Design Compiler (DC). Synthesis commands are found in scripts/synth.tcl.

Example Usage make synth DESIGN=wallypipelinedcore FREQ=500

environment variables

DESIGN Design provides the name of the output log. Default is synth.

FREQ Frequency in MHz. Default is 500

CONFIG The Wally configuration file. The default is rv32e. Examples: rv32e, rv64gc, rv32gc

TECH The target standard cell library. The default is sky130. sky90: skywater 90nm TT 25C sky130: skywater 130nm TT 25C

SAIFPOWER Controls if power analysis is driven by switching factor or RTL modelsim simulation. When enabled requires a saif file named power.saif. The default is 0. 0: switching factor power analysis 1: RTL simulation driven power analysis.