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77 lines
2.8 KiB
Systemverilog
77 lines
2.8 KiB
Systemverilog
///////////////////////////////////////////
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// swbytemask.sv
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//
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// Written: David_Harris@hmc.edu
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// Created: 9 January 2021
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// Modified: 18 January 2023
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//
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// Purpose: On-chip RAM, external to core
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//
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// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module swbytemask #(parameter WORDLEN, EXTEND = 0)(
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input logic [2:0] Size,
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input logic [$clog2(WORDLEN/8)-1:0] Adr,
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output logic [WORDLEN/8-1:0] ByteMask,
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output logic [WORDLEN/8-1:0] ByteMaskExtended
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);
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if(EXTEND) begin
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logic [WORDLEN*2/8-1:0] ExtendedByteMask;
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// 'd2 means 2, but stops Design Compiler from complaining about signed to unsigned conversion
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assign ExtendedByteMask = (('d2**('d2**Size))-'d1) << Adr;
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assign ByteMask = ExtendedByteMask[WORDLEN/8-1:0];
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assign ByteMaskExtended = ExtendedByteMask[WORDLEN*2/8-1:WORDLEN/8];
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end else begin
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assign ByteMask = (('d2**('d2**Size))-'d1) << Adr;
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assign ByteMaskExtended = '0;
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end
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/* Equivalent to the following
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if(WORDLEN == 64) begin
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always_comb begin
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case(Size[1:0])
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2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1; end // sb
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2'b01: case (Adr[2:1])
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2'b00: ByteMask = 8'b0000_0011;
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2'b01: ByteMask = 8'b0000_1100;
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2'b10: ByteMask = 8'b0011_0000;
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2'b11: ByteMask = 8'b1100_0000;
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endcase
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2'b10: if (Adr[2]) ByteMask = 8'b11110000;
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else ByteMask = 8'b00001111;
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2'b11: ByteMask = 8'b1111_1111;
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endcase
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end
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end else begin
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always_comb begin
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case(Size[1:0])
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2'b00: begin ByteMask = 4'b0000; ByteMask[Adr[1:0]] = 1; end // sb
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2'b01: if (Adr[1]) ByteMask = 4'b1100;
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else ByteMask = 4'b0011;
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2'b10: ByteMask = 4'b1111;
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default: ByteMask = 4'b1111;
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endcase
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end
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end
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*/
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endmodule
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