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437 lines
28 KiB
Systemverilog
437 lines
28 KiB
Systemverilog
/////////////////////////////////////////////////////////////////////////////////////////////////////////
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// lsu.sv
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//
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// Written: David_Harris@hmc.edu, ross1728@gmail.com
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// Created: 9 January 2021
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// Modified: 11 January 2023
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//
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// Purpose: Load/Store Unit
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// HPTW, DMMU, data cache, interface to external bus
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// Atomic, Endian swap, and subword read/write logic
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//
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// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.2)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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/////////////////////////////////////////////////////////////////////////////////////////////////////////
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module lsu import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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output logic LSUStallM, // LSU stalls pipeline during a multicycle operation
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// connected to cpu (controls)
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input logic [1:0] MemRWE, // Read/Write control
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input logic [1:0] MemRWM, // Read/Write control
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input logic [2:0] Funct3M, // Size of memory operation
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input logic [6:0] Funct7M, // Atomic memory operation function
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input logic [1:0] AtomicM, // Atomic memory operation
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input logic FlushDCacheM, // Flush D cache to next level of memory
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input logic [3:0] CMOpM, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
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input logic LSUPrefetchM, // Prefetch; presently unused
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output logic CommittedM, // Delay interrupts while memory operation in flight
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output logic SquashSCW, // Store conditional failed disable write to GPR
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output logic DCacheMiss, // D cache miss for performance counters
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output logic DCacheAccess, // D cache memory access for performance counters
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// address and write data
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input logic [P.XLEN-1:0] IEUAdrE, // Execution stage memory address
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output logic [P.XLEN-1:0] IEUAdrM, // Memory stage memory address
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input logic [P.XLEN-1:0] WriteDataM, // Write data from IEU
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output logic [P.LLEN-1:0] ReadDataW, // Read data to IEU or FPU
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// cpu privilege
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input logic [1:0] PrivilegeModeW, // Current privilege mode
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input logic BigEndianM, // Swap byte order to big endian
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input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
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output logic DCacheStallM, // D$ busy with multicycle operation
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// fpu
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input logic [P.FLEN-1:0] FWriteDataM, // Write data from FPU
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input logic FpLoadStoreM, // Selects FPU as store for write data
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// faults
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output logic LoadPageFaultM, StoreAmoPageFaultM, // Page fault exceptions
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output logic LoadMisalignedFaultM, // Load address misaligned fault
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output logic LoadAccessFaultM, // Load access fault (PMA)
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output logic HPTWInstrAccessFaultF, // HPTW generated access fault during instruction fetch
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output logic HPTWInstrPageFaultF, // HPTW generated access fault during instruction fetch
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// cpu hazard unit (trap)
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output logic StoreAmoMisalignedFaultM, // Store or AMO address misaligned fault
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output logic StoreAmoAccessFaultM, // Store or AMO access fault
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// connect to ahb
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output logic [P.PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU
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input logic [P.XLEN-1:0] HRDATA, // Bus read data from LSU to EBU
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output logic [P.XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU
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input logic LSUHREADY, // Bus ready from LSU to EBU
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output logic LSUHWRITE, // Bus write operation from LSU to EBU
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output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU
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output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU
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output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU
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output logic [P.XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU
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// page table walker
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input logic [P.XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
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input logic [1:0] STATUS_MPP, // Machine previous privilege mode
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input logic ENVCFG_PBMTE, // Page-based memory types enabled
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input logic ENVCFG_ADUE, // HPTW A/D Update enable
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input logic [P.XLEN-1:0] PCSpillF, // Fetch PC
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input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
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input logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits
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output logic [P.XLEN-1:0] PTE, // Page table entry write to ITLB
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output logic [1:0] PageType, // Type of page table entry to write to ITLB
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output logic ITLBWriteF, // Write PTE to ITLB
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output logic SelHPTW, // During a HPTW walk the effective privilege mode becomes S_MODE
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input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit
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input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0] // PMP address from privileged unit
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);
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localparam logic MISALIGN_SUPPORT = P.ZICCLSM_SUPPORTED & P.DCACHE_SUPPORTED;
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localparam MLEN = MISALIGN_SUPPORT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess
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logic [P.XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
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logic [P.XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
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logic [P.PA_BITS-1:0] PAdrM; // Physical memory address
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logic [P.XLEN+1:0] IHAdrM; // Either IEU or HPTW memory address
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logic [1:0] PreLSURWM; // IEU or HPTW Read/Write signal
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logic [1:0] LSURWM; // IEU or HPTW Read/Write signal gated by LR/SC
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logic [2:0] LSUFunct3M; // IEU or HPTW memory operation size
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logic [6:0] LSUFunct7M; // AMO function gated by HPTW
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logic [1:0] LSUAtomicM; // AMO signal gated by HPTW
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logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1
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logic BusStall; // Bus interface busy with multicycle operation
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logic HPTWStall; // HPTW busy with multicycle operation
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logic CacheBusHPWTStall; // Cache, bus, or hptw is requesting a stall
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logic SelSpillE; // Align logic detected a spill and needs to stall
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logic CacheableM; // PMA indicates memory address is cacheable
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logic BusCommittedM; // Bus memory operation in flight, delay interrupts
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logic DCacheCommittedM; // D$ memory operation started, delay interrupts
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logic [P.LLEN-1:0] DTIMReadDataWordM; // DTIM read data
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/* verilator lint_off WIDTHEXPAND */
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logic [MLEN-1:0] DCacheReadDataWordM; // D$ read data
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logic [MLEN-1:0] LSUWriteDataSpillM; // Final write data
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logic [MLEN/8-1:0] ByteMaskSpillM; // Selects which bytes within a word to write
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/* verilator lint_on WIDTHEXPAND */
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logic [P.LLEN-1:0] DCacheReadDataWordSpillM; // D$ read data
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logic [P.LLEN-1:0] ReadDataWordMuxM; // DTIM or D$ read data
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logic [P.LLEN-1:0] LittleEndianReadDataWordM; // Endian-swapped read data
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logic [P.LLEN-1:0] ReadDataWordM; // Read data before subword selection
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logic [P.LLEN-1:0] ReadDataM; // Final read data
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logic [P.XLEN-1:0] IHWriteDataM; // IEU or HPTW write data
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logic [P.XLEN-1:0] IMAWriteDataM; // IEU, HPTW, or AMO write data
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logic [P.LLEN-1:0] IMAFWriteDataM; // IEU, HPTW, AMO, or FPU write data
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logic [P.LLEN-1:0] LittleEndianWriteDataM; // Ending-swapped write data
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logic [P.LLEN-1:0] LSUWriteDataM; // Final write data
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logic [(P.LLEN-1)/8:0] ByteMaskM; // Selects which bytes within a word to write
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logic [(P.LLEN-1)/8:0] ByteMaskExtendedM; // Selects which bytes within a word to write
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logic [1:0] MemRWSpillM;
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logic SpillStallM;
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logic SelStoreDelay;
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logic DTLBMissM; // DTLB miss causes HPTW walk
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logic DTLBWriteM; // Writes PTE and PageType to DTLB
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logic DataUpdateDAM; // DTLB hit needs to update dirty or access bits
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logic LSULoadAccessFaultM; // Load acces fault
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logic LSUStoreAmoAccessFaultM; // Store access fault
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logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle
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logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation
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logic SelDTIM; // Select DTIM rather than bus or D$
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logic [P.XLEN-1:0] WriteDataZM;
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logic LSULoadPageFaultM, LSUStoreAmoPageFaultM;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Pipeline for IEUAdr E to M
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// Zero-extend address to 34 bits for XLEN=32
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/////////////////////////////////////////////////////////////////////////////////////////////
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flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
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if(MISALIGN_SUPPORT) begin : ziccslm_align
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logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
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align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M,
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.MemRWM,
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.DCacheReadDataWordM, .CacheBusHPWTStall, .SelHPTW,
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.ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM,
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.IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .DCacheReadDataWordSpillM, .SpillStallM,
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.SelStoreDelay);
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assign IEUAdrExtM = {2'b00, IEUAdrSpillM};
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assign IEUAdrExtE = {2'b00, IEUAdrSpillE};
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end else begin : no_ziccslm_align
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assign IEUAdrExtM = {2'b00, IEUAdrM};
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assign IEUAdrExtE = {2'b00, IEUAdrE};
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assign SelSpillE = '0;
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assign DCacheReadDataWordSpillM = DCacheReadDataWordM;
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assign ByteMaskSpillM = ByteMaskM;
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assign LSUWriteDataSpillM = LSUWriteDataM;
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assign MemRWSpillM = MemRWM;
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assign {SpillStallM, SelStoreDelay} = '0;
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end
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if(P.ZICBOZ_SUPPORTED) begin : cboz
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mux2 #(P.XLEN) writedatacbozmux(WriteDataM, '0, CMOpM[3], WriteDataZM);
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end else begin : cboz
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assign WriteDataZM = WriteDataM;
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end
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/////////////////////////////////////////////////////////////////////////////////////////////
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// HPTW (only needed if VM supported)
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// MMU include PMP and is needed if any privileged supported
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(P.VIRTMEM_SUPPORTED) begin : hptw
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hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
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.DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM,
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.FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_ADUE, .PrivilegeModeW,
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.ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
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.WriteDataM(WriteDataZM), .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
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.IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
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.IHAdrM, .HPTWStall, .SelHPTW,
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.IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM,
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.LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultF,
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.LoadPageFaultM, .StoreAmoPageFaultM, .LSULoadPageFaultM, .LSUStoreAmoPageFaultM, .HPTWInstrPageFaultF
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);
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end else begin // No HPTW, so signals are not multiplexed
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assign PreLSURWM = MemRWM;
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assign IHAdrM = IEUAdrExtM;
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assign LSUFunct3M = Funct3M;
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assign LSUFunct7M = Funct7M;
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assign LSUAtomicM = AtomicM;
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assign IHWriteDataM = WriteDataZM;
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assign LoadAccessFaultM = LSULoadAccessFaultM;
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assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM;
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assign LoadPageFaultM = LSULoadPageFaultM;
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assign StoreAmoPageFaultM = LSUStoreAmoPageFaultM;
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assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
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assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = '0;
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end
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// CommittedM indicates the cache, bus, or HPTW are busy with a multiple cycle operation.
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// CommittedM is 1 after the first cycle and until the last cycle. Partially completed memory
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// operations delay interrupts until the next instruction by suppressing pending interrupts in
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// the trap module.
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assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
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assign GatedStallW = StallW & ~SelHPTW;
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assign CacheBusHPWTStall = DCacheStallM | HPTWStall | BusStall;
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assign LSUStallM = CacheBusHPWTStall | SpillStallM;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// MMU and misalignment fault logic required if privileged unit exists
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(P.ZICSR_SUPPORTED == 1) begin : dmmu
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logic DisableTranslation; // During HPTW walk or D$ flush disable virtual memory address translation
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logic WriteAccessM;
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assign DisableTranslation = SelHPTW | FlushDCacheM;
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assign WriteAccessM = PreLSURWM[0];
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mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0))
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dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
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.PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]),
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.PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM),
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.PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM),
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.InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM),
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.StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM(LSULoadPageFaultM),
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.StoreAmoPageFaultM(LSUStoreAmoPageFaultM),
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.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, // *** these faults need to be supressed during hptw.
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.UpdateDA(DataUpdateDAM), .CMOpM(CMOpM),
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.AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0),
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.WriteAccessM, .ReadAccessM(PreLSURWM[1]),
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
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end else begin // No MMU, so no PMA/page faults and no address translation
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assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0;
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assign {LSULoadPageFaultM, LSUStoreAmoPageFaultM} = '0;
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assign PAdrM = IHAdrM[P.PA_BITS-1:0];
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assign CacheableM = 1'b1;
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assign SelDTIM = P.DTIM_SUPPORTED & ~P.BUS_SUPPORTED; // if no PMA then select dtim if there is a DTIM. If there is
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// a bus then this is always 0. Cannot have both without PMA.
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end
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Memory System (options)
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// 1. DTIM
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// 2. DTIM and bus
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// 3. Bus
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// 4. Cache and bus
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Pause IEU memory request if TLB miss. After TLB fill, replay request.
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// Discard memory request on pipeline flush
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assign IgnoreRequest = IgnoreRequestTLB | FlushW;
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if (P.DTIM_SUPPORTED) begin : dtim
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logic [P.PA_BITS-1:0] DTIMAdr;
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logic [1:0] DTIMMemRWM;
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// The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
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mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], MemRWM[0], DTIMAdr);
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assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0;
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// **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
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// **** create config to support DTIM with floating point.
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// Add support for cboz
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dtim #(P) dtim(.clk, .reset, .ce(~GatedStallW), .MemRWE(MemRWE), // *** update when you update the cache RWE
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.MemRWM(DTIMMemRWM),
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.DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM),
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.ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM));
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end
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if (P.BUS_SUPPORTED) begin : bus
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if(P.DCACHE_SUPPORTED) begin : dcache
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localparam LLENWORDSPERLINE = P.DCACHE_LINELENINBITS/P.LLEN; // Number of LLEN words in cacheline
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localparam LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^
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localparam BEATSPERLINE = P.DCACHE_LINELENINBITS/P.AHBW; // Number of AHBW words (beats) in cacheline
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localparam AHBWLOGBWPL = $clog2(BEATSPERLINE); // Log2 of ^
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localparam LINELEN = P.DCACHE_LINELENINBITS; // Number of bits in cacheline
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localparam LLENPOVERAHBW = P.LLEN / P.AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
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localparam CACHEWORDLEN = P.ZICCLSM_SUPPORTED ? 2*P.LLEN : P.LLEN; // Width of the cache's input and output data buses. Misaligned doubles width for fast access
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logic [LINELEN-1:0] FetchBuffer; // Temporary buffer to hold partially fetched cacheline
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logic [P.PA_BITS-1:0] DCacheBusAdr; // Cacheline address to fetch or writeback.
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logic [AHBWLOGBWPL-1:0] BeatCount; // Position within a cacheline. ahbcacheinterface to cache
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logic DCacheBusAck; // ahbcacheinterface completed fetch or writeback
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logic SelBusBeat; // ahbcacheinterface selects postion in cacheline with BeatCount
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logic [1:0] CacheBusRW; // Cache sends request to ahbcacheinterface
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logic [1:0] BusRW; // Uncached bus memory access
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logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush
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logic [1:0] CacheRWM; // Cache read (10), write (01), AMO (11)
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logic FlushDCache; // Suppress d cache flush if there is an ITLB miss.
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logic CacheStall;
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logic [1:0] CacheBusRWTemp;
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logic BusCMOZero;
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logic [3:0] CacheCMOpM;
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logic BusAtomic;
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if(P.ZICBOZ_SUPPORTED) begin
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assign BusCMOZero = CMOpM[3] & ~CacheableM;
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assign CacheCMOpM = (CacheableM & ~SelHPTW) ? CMOpM : '0;
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assign BusAtomic = AtomicM[1] & ~CacheableM;
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end else begin
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assign BusCMOZero = '0;
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assign CacheCMOpM = '0;
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assign BusAtomic = '0;
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end
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assign BusRW = ~CacheableM & ~SelDTIM ? LSURWM : '0;
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assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
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assign CacheRWM = CacheableM & ~SelDTIM ? LSURWM : '0;
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assign FlushDCache = FlushDCacheM & ~(SelHPTW);
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cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
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.NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
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.clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(FlushW | IgnoreRequestTLB),
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.CacheRW(SelStoreDelay ? 2'b00 : CacheRWM),
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.FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM),
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.ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
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.CacheWriteData(LSUWriteDataSpillM), .SelHPTW,
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.CacheStall, .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
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.CacheCommitted(DCacheCommittedM),
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.CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM),
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.FetchBuffer, .CacheBusRW(CacheBusRWTemp),
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.CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0), .CMOpM(CacheCMOpM));
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assign DCacheStallM = CacheStall & ~IgnoreRequestTLB;
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assign CacheBusRW = CacheBusRWTemp;
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// *** add support for cboz
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ahbcacheinterface #(.AHBW(P.AHBW), .LLEN(P.LLEN), .PA_BITS(P.PA_BITS), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
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.HCLK(clk), .HRESETn(~reset), .Flush(FlushW | IgnoreRequestTLB),
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.HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
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.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
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.BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM[P.LLEN-1:0]), .WriteDataM(LSUWriteDataM),
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.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .BusAtomic, .BusCMOZero, .CacheableOrFlushCacheM,
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.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
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.Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW),
|
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.BusStall, .BusCommitted(BusCommittedM));
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|
|
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// Mux between the 3 sources of read data, 0: cache, 1: Bus, 2: DTIM
|
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// Uncache bus access may be smaller width than LLEN. Duplicate LLENPOVERAHBW times.
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|
// *** DTIMReadDataWordM should be increased to LLEN.
|
|
// pma should generate exception for LLEN read to periph.
|
|
mux3 #(P.LLEN) UnCachedDataMux(.d0(DCacheReadDataWordSpillM), .d1({LLENPOVERAHBW{FetchBuffer[P.XLEN-1:0]}}),
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|
.d2({{P.LLEN-P.XLEN{1'b0}}, DTIMReadDataWordM[P.XLEN-1:0]}),
|
|
.s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM));
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end else begin : passthrough // No Cache, use simple ahbinterface instad of ahbcacheinterface
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|
logic [1:0] BusRW; // Non-DTIM memory access, ignore cacheableM
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|
logic [P.XLEN-1:0] FetchBuffer;
|
|
assign BusRW = ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
|
|
|
|
assign LSUHADDR = PAdrM;
|
|
assign LSUHSIZE = LSUFunct3M;
|
|
|
|
ahbinterface #(P.XLEN, 1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY),
|
|
.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
|
|
.HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM[P.XLEN-1:0]),
|
|
.Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
|
|
|
|
// Mux between the 2 sources of read data, 0: Bus, 1: DTIM
|
|
if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]);
|
|
else assign ReadDataWordMuxM = FetchBuffer[P.XLEN-1:0];
|
|
assign LSUHBURST = 3'b0;
|
|
assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
|
|
end
|
|
end else begin: nobus // block: bus, only DTIM
|
|
assign LSUHWDATA = '0;
|
|
assign ReadDataWordMuxM = DTIMReadDataWordM;
|
|
assign {BusStall, BusCommittedM} = '0;
|
|
assign {DCacheMiss, DCacheAccess} = '0;
|
|
assign {DCacheStallM, DCacheCommittedM} = '0;
|
|
end
|
|
|
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
|
// Atomic operations
|
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
if (P.A_SUPPORTED) begin:atomic
|
|
atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM,
|
|
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
|
|
.IMAWriteDataM, .SquashSCW, .LSURWM);
|
|
end else begin:lrsc
|
|
assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign IMAWriteDataM = IHWriteDataM;
|
|
end
|
|
|
|
if (P.F_SUPPORTED)
|
|
mux2 #(P.LLEN) datamux({{{P.LLEN-P.XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM);
|
|
else assign IMAFWriteDataM = IMAWriteDataM;
|
|
|
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
|
// Subword Accesses
|
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
|
|
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
|
|
subwordwrite #(P.LLEN) subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
|
|
|
|
// Compute byte masks
|
|
swbytemask #(P.LLEN, P.ZICCLSM_SUPPORTED) swbytemask(.Size(LSUFunct3M), .Adr(PAdrM[$clog2(P.LLEN/8)-1:0]), .ByteMask(ByteMaskM), .ByteMaskExtended(ByteMaskExtendedM));
|
|
|
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
|
// MW Pipeline Register
|
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
flopen #(P.LLEN) ReadDataMWReg(clk, ~StallW, ReadDataM, ReadDataW);
|
|
|
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
|
// Big Endian Byte Swapper
|
|
// hart works little-endian internally
|
|
// swap the bytes when read from big-endian memory
|
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
if (P.BIGENDIAN_SUPPORTED) begin:endian
|
|
endianswap #(P.LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
|
|
endianswap #(P.LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
|
|
end else begin
|
|
assign LSUWriteDataM = LittleEndianWriteDataM;
|
|
assign LittleEndianReadDataWordM = ReadDataWordMuxM;
|
|
end
|
|
endmodule
|