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51 lines
1.7 KiB
Systemverilog
51 lines
1.7 KiB
Systemverilog
///////////////////////////////////////////
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// arrs.sv
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//
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// Written: Ross Thompson ross1728@gmail.com
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// Modified: November 12, 2021
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//
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// Purpose: resets are typically asynchronous but need to be synchronized to
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// a clock to prevent changing in the invalid window clock edge.
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// arrs takes in the asynchronous reset and outputs an asynchronous
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// rising edge, but then syncs the falling edge to the posedge clk.
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module arrs(
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input logic clk,
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input logic areset,
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output logic reset
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);
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logic metaStable;
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logic resetB;
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always_ff @(posedge clk , posedge areset) begin
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if (areset) begin
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metaStable <= 1'b0;
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resetB <= 1'b0;
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end else begin
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metaStable <= 1'b1;
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resetB <= metaStable;
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end
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end
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assign reset = ~resetB;
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endmodule
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