Ross Thompson 6ccbdc372d Broken. ... Possible change to walker, dcache, tlb addressing. Improves the naming of address signals. But has a problem when the walker finishes the dcache does not get the correct address on the cycle the DTLB is updated. This leads to incorrect index selection in the dcache.		2021-07-19 10:33:27 -05:00
..
cache-sram.sv	A few more cache fixes	2021-04-13 01:07:40 -04:00
dcache.sv	Broken.	2021-07-19 10:33:27 -05:00
DCacheMem.sv	Progress towards the test bench flush.	2021-07-12 14:22:13 -05:00
dmapped.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
icache.sv	added page table walker fault exit for icache.	2021-07-01 17:59:55 -05:00
ICacheCntrl.sv	Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.	2021-07-09 15:16:38 -05:00
ICacheMem.sv	Partial implementation of the data cache. Missing the fsm.	2021-07-07 17:52:16 -05:00
sram1rw.sv	Reduced icache to 1 port memory.	2021-05-03 14:47:49 -05:00