mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-07 04:05:19 +00:00
6ccbdc372d
Possible change to walker, dcache, tlb addressing. Improves the naming of address signals. But has a problem when the walker finishes the dcache does not get the correct address on the cycle the DTLB is updated. This leads to incorrect index selection in the dcache.
423 lines
40 KiB
Plaintext
423 lines
40 KiB
Plaintext
onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/memfilename
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add wave -noupdate /testbench/dut/hart/SATP_REGW
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add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
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add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
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add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/hart/ifu/bpred/bpred/BPPredF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBValidF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPInstrClassF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBPredPCF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/RASPCF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/TargetPC
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add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/hart/ifu/bpred/bpred/BPPredE
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add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/hart/ifu/bpred/bpred/PCSrcE
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add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/hart/ifu/bpred/bpred/BPPredDirWrongE
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
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add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
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add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCE
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add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/TargetWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/FallThroughWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionPCWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/InstrClassE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionInstrClassWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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add wave -noupdate -group {instruction pipeline} /testbench/InstrW
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
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add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -group alu -divider internals
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2E
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdE
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdM
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdW
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/MemReadE
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RegWriteM
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RegWriteW
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add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/ForwardAE
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add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/ForwardBE
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add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/LoadStallD
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/WriteDataE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -group PCS /testbench/PCW
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/W64E
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallM
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallW
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/genblk1/div/start
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivDoneE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/fsm1/CURRENT_STATE
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
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add wave -noupdate -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
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add wave -noupdate -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
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add wave -noupdate -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
|
|
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
|
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
|
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
|
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
|
|
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
|
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
|
|
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
|
|
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
|
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
|
|
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
|
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
|
|
add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES
|
|
add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN
|
|
add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN
|
|
add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN
|
|
add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN
|
|
add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN
|
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
|
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
|
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
|
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
|
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
|
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
|
|
add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
|
|
add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
|
|
add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
|
|
add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
|
|
add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
|
|
add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
|
|
add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
|
|
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
|
|
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
|
|
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemSizeM
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HREADY
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESP
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDR
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWDATA
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITE
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZE
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HBURST
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HPROT
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HTRANS
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
|
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
|
|
add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWEn
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
|
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
|
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
|
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
|
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
|
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
|
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -divider data
|
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
|
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
|
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
|
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HWRITE
|
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADY
|
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HTRANS
|
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HWDATA
|
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/UARTIntr
|
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/GPIOIntr
|
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADPLIC
|
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HRESPPLIC
|
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADYPLIC
|
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/ExtIntM
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
|
|
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
|
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
|
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HSELUART
|
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HADDR
|
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HWRITE
|
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HWDATA
|
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HREADUART
|
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESPUART
|
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HREADYUART
|
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/SIN
|
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/DSRb
|
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/DCDb
|
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/CTSb
|
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/RIb
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/SOUT
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RTSb
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/DTRb
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/OUT1b
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/OUT2b
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/INTR
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb
|
|
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
|
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
|
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
|
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HCLK
|
|
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HSELUART
|
|
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR
|
|
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE
|
|
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA
|
|
TreeUpdate [SetDefaultTree]
|
|
WaveRestoreCursors {{Cursor 4} {29137 ns} 0} {{Cursor 2} {9057796 ns} 0} {{Cursor 3} {6427 ns} 0} {{Cursor 4} {8817757 ns} 0}
|
|
quietly wave cursor active 1
|
|
configure wave -namecolwidth 250
|
|
configure wave -valuecolwidth 297
|
|
configure wave -justifyvalue left
|
|
configure wave -signalnamewidth 1
|
|
configure wave -snapdistance 10
|
|
configure wave -datasetprefix 0
|
|
configure wave -rowmargin 4
|
|
configure wave -childrowmargin 2
|
|
configure wave -gridoffset 0
|
|
configure wave -gridperiod 1
|
|
configure wave -griddelta 40
|
|
configure wave -timeline 0
|
|
configure wave -timelineunits ns
|
|
update
|
|
WaveRestoreZoom {29035 ns} {29291 ns}
|