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https://github.com/openhwgroup/cvw
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84 lines
3.1 KiB
Systemverilog
84 lines
3.1 KiB
Systemverilog
///////////////////////////////////////////
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// csru.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: User-Mode Control and Status Registers for Floating Point
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//
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// Documentation: RISC-V System on Chip Design Chapter 5
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module csru import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic InstrValidNotFlushedM,
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input logic CSRUWriteM,
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input logic [11:0] CSRAdrM,
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input logic [P.XLEN-1:0] CSRWriteValM,
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input logic [1:0] STATUS_FS,
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output logic [P.XLEN-1:0] CSRUReadValM,
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input logic [4:0] SetFflagsM,
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output logic [2:0] FRM_REGW,
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output logic WriteFRMM, WriteFFLAGSM,
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output logic IllegalCSRUAccessM
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);
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localparam FFLAGS = 12'h001;
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localparam FRM = 12'h002;
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localparam FCSR = 12'h003;
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logic [4:0] FFLAGS_REGW;
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logic [2:0] NextFRMM;
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logic [4:0] NextFFLAGSM;
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logic SetOrWriteFFLAGSM;
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// Write enables
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assign WriteFRMM = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR);
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assign WriteFFLAGSM = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR);
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// Write Values
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assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];
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assign NextFFLAGSM = WriteFFLAGSM ? CSRWriteValM[4:0] : FFLAGS_REGW | SetFflagsM;
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assign SetOrWriteFFLAGSM = WriteFFLAGSM | (|SetFflagsM & InstrValidNotFlushedM);
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// CSRs
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flopenr #(3) FRMreg(clk, reset, WriteFRMM, NextFRMM, FRM_REGW);
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flopenr #(5) FFLAGSreg(clk, reset, SetOrWriteFFLAGSM, NextFFLAGSM, FFLAGS_REGW);
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// CSR Reads
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always_comb begin
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if (STATUS_FS == 2'b00) begin // fpu disabled, trap
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IllegalCSRUAccessM = 1;
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CSRUReadValM = 0;
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end else begin
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IllegalCSRUAccessM = 0;
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case (CSRAdrM)
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FFLAGS: CSRUReadValM = {{(P.XLEN-5){1'b0}}, FFLAGS_REGW};
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FRM: CSRUReadValM = {{(P.XLEN-3){1'b0}}, FRM_REGW};
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FCSR: CSRUReadValM = {{(P.XLEN-8){1'b0}}, FRM_REGW, FFLAGS_REGW};
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default: begin
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CSRUReadValM = 0;
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IllegalCSRUAccessM = 1;
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end
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endcase
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end
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end
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endmodule
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