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127 lines
6.0 KiB
Systemverilog
127 lines
6.0 KiB
Systemverilog
///////////////////////////////////////////
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// tlb.sv
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//
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// Written: jtorrey@hmc.edu 16 February 2021
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// Modified: kmacsaigoren@hmc.edu 1 June 2021
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// Implemented SV48 on top of SV39. This included adding the SvMode signal,
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// and using it to decide the translate signal and get the virtual page number
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//
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// Purpose: Translation lookaside buffer
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// Cache of virtural-to-physical address translations
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//
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// Documentation: RISC-V System on Chip Design Chapter 8
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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/**
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* SV32 specs
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* ----------
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* Virtual address [31:0] (32 bits)
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* [________________________________]
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* |--VPN1--||--VPN0--||----OFF---|
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* 10 10 12
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*
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* Physical address [33:0] (34 bits)
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* [__________________________________]
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* |---PPN1---||--PPN0--||----OFF---|
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* 12 10 12
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*
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* Page Table Entry [31:0] (32 bits)
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* [________________________________]
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* |---PPN1---||--PPN0--|||DAGUXWRV
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* 12 10 ^^
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* RSW(2) -- for OS
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*/
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// The TLB will have 2**ENTRY_BITS total entries
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module tlb import cvw::*; #(parameter cvw_t P,
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parameter TLB_ENTRIES = 8, ITLB = 0) (
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input logic clk, reset,
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input logic [P.SVMODE_BITS-1:0] SATP_MODE, // Current address translation mode
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input logic [P.ASID_BITS-1:0] SATP_ASID,
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic ENVCFG_PBMTE, // Page-based memory types enabled
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input logic ENVCFG_ADUE, // HPTW A/D Update enable
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input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
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input logic ReadAccess,
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input logic WriteAccess,
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input logic [3:0] CMOp,
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input logic DisableTranslation,
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input logic [P.XLEN-1:0] VAdr, // address input before translation (could be physical or virtual)
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input logic [P.XLEN-1:0] PTE, // page table entry to write
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input logic [1:0] PageTypeWriteVal,
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input logic TLBWrite,
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input logic TLBFlush,
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output logic [P.PA_BITS-1:0] TLBPAdr,
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output logic TLBMiss,
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output logic TLBHit,
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output logic Translate,
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output logic TLBPageFault,
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output logic UpdateDA,
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output logic [1:0] PBMemoryType // PBMT field of PTE during TLB hit, or 00 otherwise
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);
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logic [TLB_ENTRIES-1:0] Matches, WriteEnables, PTE_Gs, PTE_NAPOTs; // used as the one-hot encoding of WriteIndex
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// Sections of the virtual and physical addresses
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logic [P.VPN_BITS-1:0] VPN;
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logic [P.PPN_BITS-1:0] PPN;
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// Sections of the page table entry
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logic [11:0] PTEAccessBits;
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logic [1:0] HitPageType;
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logic CAMHit;
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logic SV39Mode;
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logic Misaligned;
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logic MegapageMisaligned;
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logic PTE_N; // NAPOT page table entry
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if(P.XLEN == 32) begin
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assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0
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assign Misaligned = (HitPageType == 2'b01) & MegapageMisaligned;
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end else begin // 64-bit
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logic GigapageMisaligned, TerapageMisaligned;
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assign TerapageMisaligned = |(PPN[26:0]); // must have zero PPN2, PPN1, PPN0
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assign GigapageMisaligned = |(PPN[17:0]); // must have zero PPN1 and PPN0
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assign MegapageMisaligned = |(PPN[8:0]); // must have zero PPN0
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assign Misaligned = ((HitPageType == 2'b11) & TerapageMisaligned) |
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((HitPageType == 2'b10) & GigapageMisaligned) |
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((HitPageType == 2'b01) & MegapageMisaligned);
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end
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assign VPN = VAdr[P.VPN_BITS+11:12];
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tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
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.PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOp, .DisableTranslation, .TLBFlush,
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.PTEAccessBits, .CAMHit, .Misaligned,
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.TLBMiss, .TLBHit, .TLBPageFault,
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.UpdateDA, .SV39Mode, .Translate, .PTE_N, .PBMemoryType);
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tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .TLBHit, .WriteEnables);
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tlbcam #(P, TLB_ENTRIES, P.VPN_BITS + P.ASID_BITS, P.VPN_SEGMENT_BITS)
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tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, .PTE_NAPOTs,
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.SATP_ASID, .Matches, .HitPageType, .CAMHit);
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tlbram #(P, TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PPN, .PTEAccessBits, .PTE_Gs, .PTE_NAPOTs);
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// Replace segments of the virtual page number with segments of the physical
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// page number. For 4 KB pages, the entire virtual page number is replaced.
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// For superpages, some segments are considered offsets into a larger page.
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tlbmixer #(P) Mixer(.VPN, .PPN, .HitPageType, .Offset(VAdr[11:0]), .TLBHit, .PTE_N, .TLBPAdr);
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endmodule
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