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https://github.com/openhwgroup/cvw
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69f6b291c6
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU. I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss. This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
368 lines
24 KiB
Systemverilog
368 lines
24 KiB
Systemverilog
/////////////////////////////////////////////////////////////////////////////////////////////////////////
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// lsu.sv
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//
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// Written: David_Harris@hmc.edu, ross1728@gmail.com
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// Created: 9 January 2021
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// Modified: 11 January 2023
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//
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// Purpose: Load/Store Unit
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// HPTW, DMMU, data cache, interface to external bus
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// Atomic, Endian swap, and subword read/write logic
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//
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// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.2)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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/////////////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module lsu (
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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output logic LSUStallM, // LSU stalls pipeline during a multicycle operation
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// connected to cpu (controls)
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input logic [1:0] MemRWM, // Read/Write control
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input logic [2:0] Funct3M, // Size of memory operation
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input logic [6:0] Funct7M, // Atomic memory operation function
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input logic [1:0] AtomicM, // Atomic memory operation
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input logic FlushDCacheM, // Flush D cache to next level of memory
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output logic CommittedM, // Delay interrupts while memory operation in flight
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output logic SquashSCW, // Store conditional failed disable write to GPR
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output logic DCacheMiss, // D cache miss for performance counters
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output logic DCacheAccess, // D cache memory access for performance counters
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// address and write data
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input logic [`XLEN-1:0] IEUAdrE, // Execution stage memory address
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output logic [`XLEN-1:0] IEUAdrM, // Memory stage memory address
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input logic [`XLEN-1:0] WriteDataM, // Write data from IEU
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output logic [`LLEN-1:0] ReadDataW, // Read data to IEU or FPU
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// cpu privilege
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input logic [1:0] PrivilegeModeW, // Current privilege mode
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input logic BigEndianM, // Swap byte order to big endian
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input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
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output logic DCacheStallM, // D$ busy with multicycle operation
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// fpu
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input logic [`FLEN-1:0] FWriteDataM, // Write data from FPU
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input logic FpLoadStoreM, // Selects FPU as store for write data
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// faults
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output logic LoadPageFaultM, StoreAmoPageFaultM, // Page fault exceptions
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output logic LoadMisalignedFaultM, // Load address misaligned fault
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output logic LoadAccessFaultM, // Load access fault (PMA)
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output logic HPTWInstrAccessFaultM, // HPTW generated access fault during instruction fetch
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// cpu hazard unit (trap)
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output logic StoreAmoMisalignedFaultM, // Store or AMO address misaligned fault
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output logic StoreAmoAccessFaultM, // Store or AMO access fault
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// connect to ahb
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output logic [`PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU
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input logic [`XLEN-1:0] HRDATA, // Bus read data from LSU to EBU
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output logic [`XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU
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input logic LSUHREADY, // Bus ready from LSU to EBU
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output logic LSUHWRITE, // Bus write operation from LSU to EBU
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output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU
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output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU
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output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU
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output logic [`XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU
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// page table walker
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input logic [`XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
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input logic [1:0] STATUS_MPP, // Machine previous privilege mode
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input logic [`XLEN-1:0] PCSpillF, // Fetch PC
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input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
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input logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits
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output logic [`XLEN-1:0] PTE, // Page table entry write to ITLB
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output logic [1:0] PageType, // Type of page table entry to write to ITLB
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output logic ITLBWriteF, // Write PTE to ITLB
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output logic SelHPTW, // During a HPTW walk the effective privilege mode becomes S_MODE
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration from privileged unit
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input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP address from privileged unit
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);
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logic [`XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
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logic [`XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
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logic [`PA_BITS-1:0] PAdrM; // Physical memory address
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logic [`XLEN+1:0] IHAdrM; // Either IEU or HPTW memory address
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logic [1:0] PreLSURWM; // IEU or HPTW Read/Write signal
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logic [1:0] LSURWM; // IEU or HPTW Read/Write signal gated by LR/SC
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logic [2:0] LSUFunct3M; // IEU or HPTW memory operation size
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logic [6:0] LSUFunct7M; // AMO function gated by HPTW
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logic [1:0] LSUAtomicM; // AMO signal gated by HPTW
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logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1
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logic BusStall; // Bus interface busy with multicycle operation
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logic HPTWStall; // HPTW busy with multicycle operation
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logic CacheableM; // PMA indicates memory address is cacheable
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logic BusCommittedM; // Bus memory operation in flight, delay interrupts
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logic DCacheCommittedM; // D$ memory operation started, delay interrupts
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logic [`LLEN-1:0] DTIMReadDataWordM; // DTIM read data
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logic [`LLEN-1:0] DCacheReadDataWordM; // D$ read data
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logic [`LLEN-1:0] ReadDataWordMuxM; // DTIM or D$ read data
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logic [`LLEN-1:0] LittleEndianReadDataWordM; // Endian-swapped read data
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logic [`LLEN-1:0] ReadDataWordM; // Read data before subword selection
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logic [`LLEN-1:0] ReadDataM; // Final read data
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logic [`XLEN-1:0] IHWriteDataM; // IEU or HPTW write data
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logic [`XLEN-1:0] IMAWriteDataM; // IEU, HPTW, or AMO write data
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logic [`LLEN-1:0] IMAFWriteDataM; // IEU, HPTW, AMO, or FPU write data
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logic [`LLEN-1:0] LittleEndianWriteDataM; // Ending-swapped write data
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logic [`LLEN-1:0] LSUWriteDataM; // Final write data
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logic [(`LLEN-1)/8:0] ByteMaskM; // Selects which bytes within a word to write
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logic DTLBMissM; // DTLB miss causes HPTW walk
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logic DTLBWriteM; // Writes PTE and PageType to DTLB
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logic DataUpdateDAM; // DTLB hit needs to update dirty or access bits
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logic LSULoadAccessFaultM; // Load acces fault
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logic LSUStoreAmoAccessFaultM; // Store access fault
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logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle
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logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation
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logic SelDTIM; // Select DTIM rather than bus or D$
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Pipeline for IEUAdr E to M
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// Zero-extend address to 34 bits for XLEN=32
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/////////////////////////////////////////////////////////////////////////////////////////////
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flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
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assign IEUAdrExtM = {2'b00, IEUAdrM};
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assign IEUAdrExtE = {2'b00, IEUAdrE};
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/////////////////////////////////////////////////////////////////////////////////////////////
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// HPTW (only needed if VM supported)
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// MMU include PMP and is needed if any privileged supported
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
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hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
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.DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM,
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.FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
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.ReadDataM(ReadDataM[`XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
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.WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
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.IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
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.IHAdrM, .HPTWStall, .SelHPTW,
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.IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM,
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.LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultM);
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end else begin // No HPTW, so signals are not multiplexed
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assign PreLSURWM = MemRWM;
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assign IHAdrM = IEUAdrExtM;
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assign LSUFunct3M = Funct3M;
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assign LSUFunct7M = Funct7M;
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assign LSUAtomicM = AtomicM;
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assign IHWriteDataM = WriteDataM;
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assign LoadAccessFaultM = LSULoadAccessFaultM;
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assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM;
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assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
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assign HPTWInstrAccessFaultM = '0;
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end
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// CommittedM indicates the cache, bus, or HPTW are busy with a multiple cycle operation.
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// CommittedM is 1 after the first cycle and until the last cycle. Partially completed memory
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// operations delay interrupts until the next instruction by suppressing pending interrupts in
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// the trap module.
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assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
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assign GatedStallW = StallW & ~SelHPTW;
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assign LSUStallM = DCacheStallM | HPTWStall | BusStall;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// MMU and misalignment fault logic required if privileged unit exists
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(`ZICSR_SUPPORTED == 1) begin : dmmu
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logic DisableTranslation; // During HPTW walk or D$ flush disable virtual memory address translation
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assign DisableTranslation = SelHPTW | FlushDCacheM;
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mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
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dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]),
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.PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM),
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.PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM),
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.InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM),
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.StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM,
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.StoreAmoPageFaultM,
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.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, // *** these faults need to be supressed during hptw.
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.UpdateDA(DataUpdateDAM),
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.AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0),
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.WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]),
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
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end else begin // No MMU, so no PMA/page faults and no address translation
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assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0;
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assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
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assign PAdrM = IHAdrM[`PA_BITS-1:0];
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assign CacheableM = 1'b1;
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assign SelDTIM = `DTIM_SUPPORTED & ~`BUS_SUPPORTED; // if no PMA then select dtim if there is a DTIM. If there is
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// a bus then this is always 0. Cannot have both without PMA.
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end
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Memory System (options)
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// 1. DTIM
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// 2. DTIM and bus
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// 3. Bus
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// 4. Cache and bus
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Pause IEU memory request if TLB miss. After TLB fill, replay request.
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// Discard memory request on pipeline flush
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assign IgnoreRequest = IgnoreRequestTLB | FlushW;
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if (`DTIM_SUPPORTED) begin : dtim
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logic [`PA_BITS-1:0] DTIMAdr;
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logic [1:0] DTIMMemRWM;
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// The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
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mux2 #(`PA_BITS) DTIMAdrMux(IEUAdrExtE[`PA_BITS-1:0], IEUAdrExtM[`PA_BITS-1:0], MemRWM[0], DTIMAdr);
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assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0;
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// **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
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// **** create config to support DTIM with floating point.
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dtim dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
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.DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM),
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.ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]));
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end else begin
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end
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if (`BUS_SUPPORTED) begin : bus
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if(`DCACHE_SUPPORTED) begin : dcache
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localparam LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN; // Number of LLEN words in cacheline
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localparam LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^
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localparam BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW; // Number of AHBW words (beats) in cacheline
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localparam AHBWLOGBWPL = $clog2(BEATSPERLINE); // Log2 of ^
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localparam LINELEN = `DCACHE_LINELENINBITS; // Number of bits in cacheline
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localparam LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
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logic [LINELEN-1:0] FetchBuffer; // Temporary buffer to hold partially fetched cacheline
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logic [`PA_BITS-1:0] DCacheBusAdr; // Cacheline address to fetch or writeback.
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logic [AHBWLOGBWPL-1:0] BeatCount; // Position within a cacheline. ahbcacheinterface to cache
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logic DCacheBusAck; // ahbcacheinterface completed fetch or writeback
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logic SelBusBeat; // ahbcacheinterface selects postion in cacheline with BeatCount
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logic [1:0] CacheBusRW; // Cache sends request to ahbcacheinterface
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logic [1:0] BusRW; // Uncached bus memory access
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logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush
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logic [1:0] CacheRWM; // Cache read (10), write (01), AMO (11)
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logic [1:0] CacheAtomicM; // Cache AMO
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logic FlushDCache; // Suppress d cache flush if there is an ITLB miss.
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assign BusRW = ~CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
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assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
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assign CacheRWM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
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assign CacheAtomicM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSUAtomicM : '0;
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assign FlushDCache = FlushDCacheM & ~(IgnoreRequestTLB | SelHPTW);
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cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
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.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .READ_ONLY_CACHE(0)) dcache(
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.clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
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.FlushCache(FlushDCache), .NextSet(IEUAdrE[11:0]), .PAdr(PAdrM),
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.ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
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.CacheWriteData(LSUWriteDataM), .SelHPTW,
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.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
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.CacheCommitted(DCacheCommittedM),
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.CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM),
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.FetchBuffer, .CacheBusRW,
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.CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
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ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
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.HCLK(clk), .HRESETn(~reset), .Flush(FlushW),
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.HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
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.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
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.BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM), .WriteDataM(LSUWriteDataM),
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.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheableOrFlushCacheM,
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.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
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.Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW),
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.BusStall, .BusCommitted(BusCommittedM));
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// Mux between the 3 sources of read data, 0: cache, 1: Bus, 2: DTIM
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// Uncache bus access may be smaller width than LLEN. Duplicate LLENPOVERAHBW times.
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// *** DTIMReadDataWordM should be increased to LLEN.
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// pma should generate exception for LLEN read to periph.
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mux3 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({LLENPOVERAHBW{FetchBuffer[`XLEN-1:0]}}),
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.d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}),
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.s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM));
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end else begin : passthrough // No Cache, use simple ahbinterface instad of ahbcacheinterface
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logic [1:0] BusRW; // Non-DTIM memory access, ignore cacheableM
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logic [`XLEN-1:0] FetchBuffer;
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assign BusRW = ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
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assign LSUHADDR = PAdrM;
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assign LSUHSIZE = LSUFunct3M;
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ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY),
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.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
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.HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM),
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.Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
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// Mux between the 2 sources of read data, 0: Bus, 1: DTIM
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if(`DTIM_SUPPORTED) mux2 #(`XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMuxM);
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else assign ReadDataWordMuxM = FetchBuffer[`XLEN-1:0];
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assign LSUHBURST = 3'b0;
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assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
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end
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end else begin: nobus // block: bus, only DTIM
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assign LSUHWDATA = '0;
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assign ReadDataWordMuxM = DTIMReadDataWordM;
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assign {BusStall, BusCommittedM} = '0;
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assign {DCacheMiss, DCacheAccess} = '0;
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assign {DCacheStallM, DCacheCommittedM} = '0;
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end
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|
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Atomic operations
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/////////////////////////////////////////////////////////////////////////////////////////////
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if (`A_SUPPORTED) begin:atomic
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atomic atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[`XLEN-1:0]), .IHWriteDataM, .PAdrM,
|
|
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
|
|
.IMAWriteDataM, .SquashSCW, .LSURWM);
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end else begin:lrsc
|
|
assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign IMAWriteDataM = IHWriteDataM;
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|
end
|
|
|
|
if (`F_SUPPORTED)
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mux2 #(`LLEN) datamux({{{`LLEN-`XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM);
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else assign IMAFWriteDataM = IMAWriteDataM;
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|
|
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
|
// Subword Accesses
|
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
|
subwordread subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
|
|
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
|
|
subwordwrite subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
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|
|
|
// Compute byte masks
|
|
swbytemask #(`LLEN) swbytemask(.Size(LSUFunct3M), .Adr(PAdrM[$clog2(`LLEN/8)-1:0]), .ByteMask(ByteMaskM));
|
|
|
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
|
// MW Pipeline Register
|
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
flopen #(`LLEN) ReadDataMWReg(clk, ~StallW, ReadDataM, ReadDataW);
|
|
|
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
|
// Big Endian Byte Swapper
|
|
// hart works little-endian internally
|
|
// swap the bytes when read from big-endian memory
|
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
if (`BIGENDIAN_SUPPORTED) begin:endian
|
|
endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
|
|
endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
|
|
end else begin
|
|
assign LSUWriteDataM = LittleEndianWriteDataM;
|
|
assign LittleEndianReadDataWordM = ReadDataWordMuxM;
|
|
end
|
|
|
|
endmodule
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