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65 lines
3.1 KiB
Systemverilog
65 lines
3.1 KiB
Systemverilog
///////////////////////////////////////////
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// forward.sv
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//
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// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu
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// Created: 9 January 2021
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// Modified:
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//
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// Purpose: Determine datapath forwarding
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//
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// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.2.2.3)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module forward(
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// Detect hazards
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input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, // Source and destination registers
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input logic MemReadE, MDUE, CSRReadE, // Execute stage instruction is a load (MemReadE), divide (MDUE), or CSR read (CSRReadE)
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input logic RegWriteM, RegWriteW, // Instruction in Memory or Writeback stage writes register file
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input logic FCvtIntE, // FPU convert float to int
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input logic SCE, // Store Conditional instruction
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// Forwarding controls
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output logic [1:0] ForwardAE, ForwardBE, // Select signals for forwarding multiplexers
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output logic FCvtIntStallD, LoadStallD, MDUStallD, CSRRdStallD // Stall due to conversion, load, multiply/divide, CSR read
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);
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logic MatchDE; // Match between a source register in Decode stage and destination register in Execute stage
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always_comb begin
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ForwardAE = 2'b00;
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ForwardBE = 2'b00;
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if (Rs1E != 5'b0)
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if ((Rs1E == RdM) & RegWriteM) ForwardAE = 2'b10;
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else if ((Rs1E == RdW) & RegWriteW) ForwardAE = 2'b01;
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if (Rs2E != 5'b0)
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if ((Rs2E == RdM) & RegWriteM) ForwardBE = 2'b10;
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else if ((Rs2E == RdW) & RegWriteW) ForwardBE = 2'b01;
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end
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// Stall on dependent operations that finish in Mem Stage and can't bypass in time
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assign MatchDE = ((Rs1D == RdE) | (Rs2D == RdE)) & (RdE != 5'b0); // Decode-stage instruction source depends on result from execute stage instruction
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assign FCvtIntStallD = FCvtIntE & MatchDE; // FPU to Integer transfers have single-cycle latency except fcvt
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assign LoadStallD = (MemReadE|SCE) & MatchDE;
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assign MDUStallD = MDUE & MatchDE; // Int mult/div is at least two cycle latency, even when coming from the FDIV
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assign CSRRdStallD = CSRReadE & MatchDE;
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endmodule
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