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170 lines
10 KiB
Systemverilog
170 lines
10 KiB
Systemverilog
///////////////////////////////////////////
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// busfsm.sv
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//
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// Written: Ross Thompson ross1728@gmail.com
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// Created: December 29, 2021
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// Modified: 18 January 2023
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//
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// Purpose: Controller for cache to AHB bus interface
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//
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// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// HCLK and clk must be the same clock!
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module buscachefsm #(
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parameter BeatCountThreshold, // Largest beat index
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parameter AHBWLOGBWPL, // Log2 of BEATSPERLINE
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parameter READ_ONLY_CACHE, // 1 for read-only instruction cache
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parameter BURST_EN // burst mode supported
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)(
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input logic HCLK,
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input logic HRESETn,
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// IEU interface
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input logic Stall, // Core pipeline is stalled
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input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
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input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write
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input logic BusAtomic, // Uncache atomic memory operation
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input logic BusCMOZero, // Uncached cbo.zero must write zero to full sized cacheline without going through the cache
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output logic BusStall, // Bus is busy with an in flight memory operation
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output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
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// ahb cache interface locals.
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output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA
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// cache interface
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input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
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output logic CacheBusAck, // Handshack to $ indicating bus transaction completed
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// lsu interface
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output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase
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output logic [AHBWLOGBWPL-1:0] BeatCountDelayed, // Beat within the cache line in the second (Data) cache stage
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output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
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// BUS interface
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input logic HREADY, // AHB peripheral ready
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output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
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output logic HWRITE, // AHB 0: Read operation 1: Write operation
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output logic [2:0] HBURST // AHB burst length
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);
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typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, ATOMIC_READ_DATA_PHASE, ATOMIC_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype;
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typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
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busstatetype CurrState, NextState;
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logic [AHBWLOGBWPL-1:0] NextBeatCount;
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logic FinalBeatCount;
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logic [2:0] LocalBurstType;
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logic BeatCntEn;
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logic BeatCntReset;
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logic CacheAccess;
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logic BusWrite;
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assign BusWrite = (CacheBusRW[0] | BusCMOZero) & ~READ_ONLY_CACHE;
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always_ff @(posedge HCLK)
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if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
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else CurrState <= #1 NextState;
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always_comb begin
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case(CurrState)
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ADR_PHASE: if (HREADY & |BusRW) NextState = DATA_PHASE; // exclusion-tag: buscachefsm HREADY0
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else if (HREADY & BusWrite & ~READ_ONLY_CACHE) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm HREADY1
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else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH; // exclusion-tag: buscachefsm HREADYread
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else NextState = ADR_PHASE;
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DATA_PHASE: if(HREADY & BusAtomic & ~READ_ONLY_CACHE) NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm HREADY2
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else if(HREADY & ~BusAtomic) NextState = MEM3; // exclusion-tag: buscachefsm HREADY3
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else NextState = DATA_PHASE;
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ATOMIC_READ_DATA_PHASE: if(HREADY) NextState = ATOMIC_PHASE; // exclusion-tag: buscachefsm AtomicReadData
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else NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm AtomicElse
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ATOMIC_PHASE: if(HREADY) NextState = MEM3; // exclusion-tag: buscachefsm AtomicPhase
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else NextState = ATOMIC_PHASE; // exclusion-tag: buscachefsm AtomicWait
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MEM3: if(Stall) NextState = MEM3;
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else NextState = ADR_PHASE;
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CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm FetchWriteback
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else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; // exclusion-tag: buscachefsm FetchWait
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else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE;
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else NextState = CACHE_FETCH;
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CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm WritebackWriteback
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else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; // exclusion-tag: buscachefsm HREADY4
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else if(HREADY & FinalBeatCount & BusCMOZero) NextState = MEM3; // exclusion-tag: buscachefsm HREADY5
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else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE; // exclusion-tag: buscachefsm HREADY6
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else NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm WritebackWriteback2
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default: NextState = ADR_PHASE;
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endcase
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end
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// IEU, LSU, and IFU controls
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// Used to store data from data phase of AHB.
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flopenr #(AHBWLOGBWPL) BeatCountReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, NextBeatCount, BeatCount);
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flopenr #(AHBWLOGBWPL) BeatCountDelayedReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, BeatCount, BeatCountDelayed);
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assign NextBeatCount = BeatCount + 1'b1;
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assign FinalBeatCount = BeatCountDelayed == BeatCountThreshold[AHBWLOGBWPL-1:0];
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assign BeatCntEn = (((NextState == CACHE_WRITEBACK | NextState == CACHE_FETCH) & HREADY & ~Flush) |
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(NextState == ADR_PHASE & |CacheBusRW & HREADY)) & ~Flush;
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assign BeatCntReset = NextState == ADR_PHASE;
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assign CaptureEn = (CurrState == DATA_PHASE & BusRW[1] & ~Flush) | (CurrState == CACHE_FETCH & HREADY);
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assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK;
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assign BusStall = (CurrState == ADR_PHASE & ((|BusRW) | (|CacheBusRW) | BusCMOZero)) |
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//(CurrState == DATA_PHASE & ~BusRW[0]) | // *** replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem.
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(CurrState == DATA_PHASE) |
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(CurrState == ATOMIC_PHASE) |
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(CurrState == ATOMIC_READ_DATA_PHASE) |
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(CurrState == CACHE_FETCH & ~FinalBeatCount) |
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(CurrState == CACHE_WRITEBACK & ~FinalBeatCount);
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assign BusCommitted = (CurrState != ADR_PHASE) & ~(READ_ONLY_CACHE & CurrState == MEM3);
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// AHB bus interface
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW) | BusCMOZero) & ~Flush) |
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(CurrState == ATOMIC_READ_DATA_PHASE) |
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(CacheAccess & FinalBeatCount & |CacheBusRW & HREADY & ~Flush) ? AHB_NONSEQ : // if we have a pipelined request
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(CacheAccess & |BeatCount) ? (BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
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assign HWRITE = (((BusRW[0] & ~BusAtomic) | BusWrite & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) |
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(CurrState == CACHE_WRITEBACK & |BeatCount)) & ~READ_ONLY_CACHE;
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assign HBURST = BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0;
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always_comb begin
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case(BeatCountThreshold)
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0: LocalBurstType = 3'b000;
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3: LocalBurstType = 3'b011; // INCR4
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7: LocalBurstType = 3'b101; // INCR8
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15: LocalBurstType = 3'b111; // INCR16
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default: LocalBurstType = 3'b001; // INCR without end.
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endcase
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end
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// communication to cache
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assign CacheBusAck = (CacheAccess & HREADY & FinalBeatCount & ~BusCMOZero);
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assign SelBusBeat = (CurrState == ADR_PHASE & (BusRW[0] | BusWrite)) |
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(CurrState == DATA_PHASE & BusRW[0]) |
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(CurrState == ATOMIC_PHASE & BusRW[0]) |
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(CurrState == ATOMIC_READ_DATA_PHASE & BusRW[0]) |
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(CurrState == CACHE_WRITEBACK) |
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(CurrState == CACHE_FETCH);
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endmodule
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