mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-24 21:44:29 +00:00
dfd07a57fd
The defaults are used for synthesis. rv64i and rv32i: DTIM 2KiB, IROM 2KiB rv32ic: DTIM 4KiB, IROM 16KiB Regression tests require 8MiB or larger so modelsim overrides. |
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.. | ||
buildroot | ||
fpga | ||
rv32e | ||
rv32gc | ||
rv32i | ||
rv32ic | ||
rv64BP | ||
rv64fpquad | ||
rv64gc | ||
rv64i | ||
shared |