mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
90 lines
1.4 KiB
C
90 lines
1.4 KiB
C
//Read the documentation before changing values
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`define BIG_ENDIAN
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//`define LITLE_ENDIAN
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`define SIM
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//`define SYN
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`define SDC_IRQ_ENABLE
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`define ACTEL
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//`define CUSTOM
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//`define ALTERA
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//`define XLINX
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//`define SIMULATOR
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`define RESEND_MAX_CNT 3
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//MAX 255 BD
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//BD size/4
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`ifdef ACTEL
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`define BD_WIDTH 5
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`define BD_SIZE 32
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`define RAM_MEM_WIDTH_16
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`define RAM_MEM_WIDTH 16
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`endif
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//`ifdef CUSTOM
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// `define NR_O_BD_4
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// `define BD_WIDTH 5
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// `define BD_SIZE 32
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// `define RAM_MEM_WIDTH_32
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// `define RAM_MEM_WIDTH 32
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//`endif
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`ifdef SYN
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`define RESET_CLK_DIV 0
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`define MEM_OFFSET 4
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`endif
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`ifdef SIM
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`define RESET_CLK_DIV 0
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`define MEM_OFFSET 4
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`endif
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//SD-Clock Defines ---------
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//Use bus clock or a seperate clock
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`define SDC_CLK_BUS_CLK
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//`define SDC_CLK_SEP
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// Use of internal clock divider
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//`define SDC_CLK_STATIC
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`define SDC_CLK_DYNAMIC
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//SD DATA-transfer defines---
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`define BLOCK_SIZE 512
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`define SD_BUS_WIDTH_4
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`define SD_BUS_W 4
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//at 512 bytes per block, equal 1024 4 bytes writings with a bus width of 4, add 2 for startbit and Z bit.
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//Add 18 for crc, endbit and z.
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`define BIT_BLOCK 1044
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`define CRC_OFF 19
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`define BIT_BLOCK_REC 1024
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`define BIT_CRC_CYCLE 16
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//FIFO defines---------------
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`define FIFO_RX_MEM_DEPTH 8
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`define FIFO_RX_MEM_ADR_SIZE 4
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`define FIFO_TX_MEM_DEPTH 8
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`define FIFO_TX_MEM_ADR_SIZE 4
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//---------------------------
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